ADS1174IPAPR datasheet(13/35 Pages) TI

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ANALOG INPUTS (AINP, AINN)

ESDProtection

AVDD

AGND

AVDD

AINP

9pF

AINN

AGND

OFF

SAMPLE

MOD

=1/f

AINP

AINN

=14k

eff

W ´ (6.75MHz/f

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

The ADS1174/78 measures each differential input

signal VIN = (AINP – AINN) against the common

differential reference VREF = (VREFP – VREFN). The

most positive measurable differential input is +VREF,

which produces the most positive digital output code

of 7FFFh. Likewise, the most negative measurable

differential input is –VREF, which produces the most

negative digital output code of 8000h.

For

optimum

performance,

the

inputs

the

ADS1174/78 are intended to be driven differentially.

For single-ended input applications, one of the inputs

(AINP or AINN) can be driven while the other input is

fixed (typically, to AGND or +2.5V); fixing the input to

+2.5V permits bipolar operation, thereby using the full

range of the converter.

Figure 7. Equivalent Analog Input Circuitry

While the ADS1174/78 measures the differential input

signal, the absolute input voltage is also important.

This is the voltage on either input (AINP or AINN)

with respect to AGND. The range for this voltage is:

–0.1V < (AINN or AINP) < AVDD + 0.1V

If either input is taken below –0.4V or above (AVDD +

0.4), ESD protection diodes on the inputs may turn

Figure 8. S1 and S2 Switch Timing for Figure 7

on.

If these conditions are possible, external Schottky

clamp diodes or series resistors may be required to

Table 4. Modulator Frequency (fMOD) versus Mode

limit the input current to safe levels (see Absolute

Selection

Maximum Ratings table).

MODE SELECTION

CLKDIV

fMOD

The ADS1174/78 is a high-performance ADC. For

fCLK/8

High-Speed

optimum performance, it is critical that the appropriate

fCLK/4

circuitry be used to drive the ADS1174/78 inputs. See

fCLK/40

the

Applications

Information

section

for

the

Low-Power

fCLK/8

recommended circuits.

The ADS1174/78 uses switched-capacitor circuitry to

The

average

load

presented

the

switched

measure the input voltage. Internal capacitors are

capacitor input can be modeled with an effective

charged by the inputs and then discharged. Figure 7

differential impedance, as shown in Figure 9. Note

shows a conceptual diagram of these circuits. Switch

that the effective impedance is a function of fMOD.

S2 represents the net effect of the modulator circuitry

in discharging the sampling capacitor; the actual

implementation is different. The timing for switches S1

and S2 is shown in Figure 8. The sampling time

(tSAMPLE) is the inverse of modulator sampling

frequency (fMOD) and is a function of the mode, the

CLKDIV input, and frequency of CLK, as shown in

Table 4.

Figure 9. Effective Input Impedances

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