HT82K96E

Rev. 2.00

24

October 11, 2007

The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference

voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal

power supplies of MCU (VDD and VSS). The VRL and VRH are used to set the minimal and maximal boundaries of the

full-scale range of the A/D converter. If an analog inputs, VRL or VRH is not used for A/D conversion, it also can be used

as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the configu-

rations and A/D clock sources of A/D converter and control the operation of A/D converter.

Bit No.

Label

Function

2~0

ACS2~ACS0

These 3 bits are use to select one of eight A/D converter channels for the conversion.

The A/D converter input channels AN0~AN5 are pin-shared with PB0~PB5. PB6/VRL

and PB7/VRH are used for the A/D converter reference inputs. ACS2,ACS1,ACS0 :

000/001/010/011/100/101/110/111: AN0/AN1/AN2/AN3/AN4/AN5/VRL/VRH

4

3

ADCS1

ADCS0

A/D converter clock source selection. ADCS1,ADCS0:

00: 6MHz

01: 3MHz

10: 1.5MHz

11: 0.75MHz

5

START

Start the A/D conversion. (0

®1®0: start, 0®1: reset A/D converter and A/D data regis-

ter)

6

ADON

This bit is used to control the enable/disable of A/D converter circuit. If this bit is set to

²1² the A/D converter enters operating mode. Otherwise, the A/D converter will be

turned-off

7

EOCB

End of A/D conversion indication. (0: end of A/D conversion)

ADSC (1DH) Register

The A/D converter data register is used to store the result of A/D conversion.

Bit No.

Label

Function

7~0

D7~D0

Result of A/D conversion

ADR (1EH) Register

Mask Options

The following table shows all kinds of mask option in the microcontroller. All of the mask options must be defined to en-

sure proper system functioning.

No.

Option

1

Chip lock bit (by bit)

2

PA0~PA7 pull-high resistor enabled or disabled (by bit)

3

PA0~PA5 pull down resistor enabled or disabled (by bit)

4

PB0~PB7 pull-high resistor enabled or disabled (by nibble)

5

PC0~PC7 pull-high resistor enabled or disabled (by nibble)

6

PD0~PD7 pull-high resistor enabled or disabled (by nibble)

7

LVR enable or disable

8

WDT enable or disable

9

10

²CLRWDT² instruction(s): 1 or 2

11

PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain (by bit)

12

PA0~PA7 wake-up enabled or disabled (by bit)

13

A/D converter enabled or disabled