HT82K96E datasheet(11/44 Pages) HOLTEK

11 / 44 page

HT82K96E

Rev. 2.00

October 11, 2007

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the

²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine,

²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an in-

terrupt service, but RET will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

No.

Interrupt Source

Priority Vector

USB interrupt

04H

Timer/Event Counter 0 overflow

08H

Timer/Event Counter 1 overflow

0CH

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F), USB interrupt request flag (USBF), enable

Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-

able USB interrupt bit (EUI) and enable master interrupt

bit (EMI) constitute an interrupt control register (INTC)

which is located at 0BH in the data memory. EMI, EUI,

ET0I and ET1I are used to control the enabling/dis-

abling of interrupts. These bits prevent the requested in-

terrupt from being serviced. Once the interrupt request

flags (T0F, T1F, USBF) are set, they will remain in the

INTC register until the interrupts are serviced or cleared

by a software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. In-

terrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications.

If only one stack is left and enabling the interrupt is not

well controlled, the original control sequence will be dam-

aged once the

²CALL² operates in the interrupt subrou-

tine.

Oscillator Configuration

There is an oscillator circuits in the microcontroller.

This oscillator is designed for system clocks. The HALT

mode stops the system oscillator and ignores an exter-

nal signal to conserve power.

A crystal across OSC1 and OSC2 is needed to provide

the feedback and phase shift required for the oscillator.

No other external components are required. In stead of

a crystal, a resonator can also be connected between

OSC1 and OSC2 to get a frequency reference, but two

external capacitors in OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works within

a period of approximately 31

ms. The WDT oscillator can

be disabled by ROM code option to conserve power.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator), or instruction clock (sys-

tem clock divided by 4), determines the ROM code op-

tion. This timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The Watchdog

Timer can be disabled by ROM code option. If the

Watchdog Timer is disabled, all the executions related

to the WDT result in no operation.

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

R O M

C o d e

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

C r y s t a l O s c i l l a t o r

O S C 2

O S C 1

System Oscillator

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