HT82K96E

Rev. 2.00

23

October 11, 2007

The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select

serial bus (PS2 or USB) and A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF, EP2IF and

EP3IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request

flag will be set to

²1² and the USB interrupt will occur (if USB interrupt is enabled and the stack is not full). When the ac-

tive endpoint request flag is served, the endpoint request flag has to be cleared to

²0².

Bit No.

Label

R/W

Function

0

EP0IF

R/W

When this bit is set to

²1² (set by SIE), it indicates the endpoint 0 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

1

EP1IF

R/W

When this bit is set to

²1² (set by SIE), it indicates the endpoint 1 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

2

EP2IF

R/W

When this bit is set to

²1² (set by SIE), it indicates the endpoint 2 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

3

EP3IF

R/W

When this bit is set to

²1² (set by SIE), it indicates the endpoint 3 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

4

SPS2

R/W The PS2 function is selected when this bit is set to

²1². (Default=²0²)

5

SUSB

R/W The USB function is selected when this bit is set to

²1². (Default=²0²)

6

ADREF

R/W

The reference voltage of A/D converter is coming from the VDD and VSS of MCU

when this bit is set

²1². Otherwise, the reference voltage of A/D converter comes

from external PB6/VRL and PB7/VRH pins. (Default=

²1²)

7

FIFO-cntl

W

For ICE only, 0 for FIFO read (Default=

²0²); 1 for FIFO write

USR (1BH) Register

There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB

clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK).

Bit No.

Label

R/W

Function

2~0

Led_on Period R/W

To define low pulse period of IRPT (PC0) for mouse hardware function.

The time base is 31.25

ms (1/32kHz). Default value is 000.

000: 2

´base

001: 3

´base

010: 5

´base

011: 9

´base

100: 17

´base

101: 33

´base

110: 65

´base

111: 127

´base

3

USBCKEN

R/W

USB clock control bit. When this bit is set to

²1², it indicates that the USB clock is

enabled. Otherwise, the USB clock is turned-off. (Default=

²0²)

4

SUSP2

R/W

This bit is used for decreasing power consumption in suspend mode.

In normal mode clean this bit=0 (Default=

²0²)

In HALT mode set this bit=1 for decreasing power consumption.

5

¾

R/W Undefined, should be cleared to

²0²

6

SYSCLK

R/W

This bit is used to specify the system oscillator frequency used by MCU. If a

6MHz crystal oscillator or resonator is used, this bit should be set to

²1².Ifa

12MHz crystal oscillator or resonator is used, this bit should be cleared to

²0² (de-

fault).

7

HWKUPSB

R/W

Hardware HALT mode wake-up detect circuit active under power down mode.

Low active.

²0²: WDT timer overflow will wake-up MCU system

²1²: WDT timer overflow will start hardware wake-up detect circuit but not

wake-up MCU system.

SCC (1CH) Register