HT82K96E

Rev. 2.00

20

October 11, 2007

The following is A/D converter timing diagrams

USB Interface and A/D Converter

There are 7 registers, including AWR (address + remote wake up; 42H in bank 1), STALL (43H in bank 1), PIPE (44H in

bank 1), MISC (46H in bank 1), FIFO0 (48H in bank 1), FIFO1 (49H in bank 1), FIFO2 (4AH in bank 1) and FIFO3 (4BH

in bank 1) used for the USB function. AWR register contains current address and a remote wake up function control bit.

The initial value of AWR is

²00H². The address value extracted from the USB command has not to be loaded into this

register until the SETUP stage being finished.

Bit No.

Label

R/W

Function

0

WKEN

W

Remote wake-up enable/disable

7~1

AD6~AD0

W

USB device address

AWR (42H) Register

PIPE register represents whether the corresponding endpoint is accessed by host or not. This register is set only after

the time when host accesses the corresponding endpoint. Only the last accessed endpoint is shown in this register.

STALL register shows whether the corresponding endpoint works properly or not. As soon as the endpoint works im-

properly, the related bit in the STALL has to be set to

²1². The STALL will be cleared by USB reset signal.

Bit No.

Label

R/W

Function

0

STL0

W

Stall the endpoint 0

1

STL1

W

Stall the endpoint 1

2

STL2

W

Stall the endpoint 2

3

STL3

W

Stall the endpoint 3

7~4

¾

W

Unused bit, read as

²0²

STALL (43H) Register

Bit No.

Label

R/W

Function

0

EP0RW

R

Endpoint 0 accessed

1

EP1RW

R

Endpoint 1 accessed

2

EP2RW

R

Endpoint 2 accessed

3

EP3RW

R

Endpoint 3 accessed

7~4

¾

R

Unused bit, read as

²0²

PIPE (44H) Register

T 1

N o r m a l M o d e

A / D C o n v e r s i o n S t a r t s

A / D C o n v e r s i o n S t a r t s

A / D C o n v e r s i o n

A / D C o n v e r s i o n T i m e

A / D C o n v e r s i o n F i n i s h e d

P o w e r _ d o w n

A / D C o n v e r s i o n F i n i s h e d

0 o r 1

0 o r 1

A / D C o n v e r s i o n

A / D C o n v e r s i o n T i m e

0 o r 1

0 o r 1

A D O N

S T A R T

D 7

D 0

E O C B

0

0

0

1