HT82K96E datasheet(17/44 Pages) HOLTEK

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HT82K96E

Rev. 2.00

October 11, 2007

Input/Output Ports

There are 32 bidirectional input/output lines in the

microcontroller, labeled from PA to PD, which are

mapped to the data memory of [12H], [14H], [16H] and

[18H] respectively. All of these I/O ports can be used for

input and output operations. For input operation, these

ports are non-latching, that is, the inputs must be ready

at the T2 rising edge of instruction

²MOV A,[m]² (m=12H,

14H, 16H or 18H). For output operation, all the data is

latched and remains unchanged until the output latch is

rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS/NMOS/PMOS output

or Schmitt trigger input with or without pull-high/low re-

sistor structures can be reconfigured dynamically (i.e.

on-the-fly) under software control. To function as an in-

put, the corresponding latch of the control register must

write

²1². The input source also depends on the control

²1², the input will

read the pad state. If the control register bit is

²0², the

contents of the latches will move to the internal bus. The

latter is possible in the

²read-modify-write² instruction.

For output function, CMOS/NMOS/PMOS configura-

tions can be selected (NMOS and PMOS are available

for PA only). These control registers are mapped to loca-

tions 13H, 15H, 17H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on the pull-high/low

options). Each bit of these input/output latches can be

set or cleared by

²SET [m].i² and ²CLR [m].i² (m=12H,

14H, 16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device.

There are pull-high/low (PA only) options available for

I/O lines. Once the pull-high/low option of an I/O line is

selected, the I/O line have pull-high/low resistor. Other-

wise, the pull-high/low resistor is absent. It should be

noted that a non-pull-high/low I/O line operating in input

mode will cause a floating state.

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

V D D

P A 0 ~ P A 5 , P A 6 / T M R 0 , P A 7 / T M R 1

P B 0 / A N 0 ~ P B 5 / A N 5

P B 6 / V R L , P B 7 / V R H

P C 0 ~ P C 7

P D 0 ~ P D 7

P G 0 ~ P G 2

P A W a k e - u p O p t i o n

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P H

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P L

P A W a k e - u p

P A 6 / T M R 0

P A 7 / T M R 1

A N 0 ~ A N 5 , V R L , V R H

P A O u t p u t

C o n f i g u r a t i o n

C K

Input/Output Ports

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