16

Notes:

1. Reference Figure 11 for clock output loading circuit that is equivalent to the load circuit used for all AC testing.

2. Supplied as a design guideline. Neither guaranteed nor tested.

is valid with stable power supplies which are within normal operating limits.

6. Lock detector circuit will monitor the phase alignment between the XTAL1 and FB inputs. When the phase separation between these two inputs is greater than the

amount listed, then the LOCK pin will drop low signaling that the PLL is out of lock.

7. This parameter is guaranteed by measuring cycle-cycle jitter on 55,000, back-to-back clock cycles.

8. Guaranteed by characterization, but not tested.

7

Cycle-cycle jitter

Divide by 1 output frequency,

FB = divide by 12

--

50

ps

Symbol

Description

Condition

Min.

Max.

Unit