9

4PD/DIV

I

3-Level

Power down and reference divider control.

This dual function pin controls the

power down operation and selects the input reference divider. Holding the pin low

during power up ensures clean RadClock startup that is independent of the behavior

of the reference clock. The pin may also be driven low at any time to force a reset

to the PLL. The following table summarizes the operating states controlled by the

PD/DIV pin.

PD/DIV

Operating Mode

Input Reference Divider

LOW

Powered Down

N/A

MID

Normal Operation

HIGH

Normal Operation

20

LOCK

O

LVTTL

PLL lock indication signal.

not be synchronized to the input. As the following table indicates, the level of phase

alignment between XTAL1 and FB that will cause the LOCK pin to change states is

dependent upon the frequency range selected by the FS input.

FS

LOCK Resolution

L

1.6ns typical

M

1.6ns typical

H

800ps typical

** Note: The LOCK pin can only be considered as a valid output when the RadClock

is in a normal mode of operation (e.g. PD/DIV != LOW, TEST = LOW, and a valid

reference clock is supplied to the XTAL1 input). Until these conditions are met,

RadClock is not in a normal operating mode and the LOCK pin may be HIGH or

LOW and therefore should not be used in making any logical decisions until the

specification to determine the delay for the LOCK pin to become valid HIGH

following a stable input reference clock and the application of a clock to the FB input.

43

2

PWR

Power

Power supply for Bank 4 output buffers.

Please see Table 12 for supply level constraints.

7

2

PWR

Power

Power supply for Bank 3 output buffers.

Please see Table 12 for supply level constraints.

19, 30

2

PWR

Power

Power supply for Bank 1 and Bank 2 output buffers.

Please see Table 12 for supply level constraints.

6, 12, 14,

35, 38

2

PWR

Power

Power supply for internal circuitry.

Please see Table 12 for supply level constraints.

10, 11, 15,

16, 21, 29,

33, 34, 39,

40, 44, 45

PWR

Power

Ground

Flatpack

Pin No.

Name

I/O

Type

Description

Notes:

1. When TEST = MID and sOE = HIGH, the PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew

selections remain in effect unless nF[1:0] = LL.

2. A bypass capacitor (0.1

μF) should be placed as close as possible to each positive power pin (<0.2"). An additional 1μF capacitor should be located within 0.2"

istics will be cancelled by the parasitic inductance of the traces. Additionally, it is recommend that wide traces (0.025" or wider) be used when connecting the

decoupling capacitors to their respective power pins on the RadClock.