5

Notes:

1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH.

2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversion-

options function as defined in Table 9.

3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these out-

puts HIGH when PE/HD = HIGH or MID, sOE disables them LOW when

PE/HD = LOW.

of skew steps. Supplied as a design limit, but not tested or guaranteed.

A graphical summary of Table 10 is shown in Figure 3. The

drawing assumes that the FB input is driven by a clock output

programmed with zero skew. Depending upon the state of the

nF[1:0] pins the respective clocks will be skewed, divided, or

inverted relative to the fedback output as shown in Figure 3.

1.3 Output Drive, Synchronization, and Power Supplies:

The UT7R995/C employs flexible output buffers providing the

user with selectable drive strengths, independent power sup-

plies, and synchronization to either edge of the reference input.

Using the 3-level PE/HD pin, the user selects the reference edge

synchronization and the output drive strength for all clock out-

puts. The options for edge synchronization and output drive

strength selected by the PE/HD pin are listed in Table 11.

Notes:

nF[1:0]

Skew

1Q[1:0], 2Q[1:0]

Skew

3Q[1:0]

Skew

4Q[1:0]

Divide by 2

Divide by 2

LM

LH

ML

MM

Zero Skew

Zero Skew

Zero Skew

MH

HL

HM

Divide by 4

Table 11: PE/HD Settings

PE/HD

Synchronization

Output Drive

L

Negative

Low Drive

M

Positive

High Drive

H

Positive

Low Drive

XTAL1 Input

FB Input

DIVIDED

INVERTED

1F[1:0]

2F[1:0]

3F[1:0]

4F[1:0]

(N/A)

(N/A)

LM

LM

LL

LL

LH

LH

LM

LM

(N/A)

(N/A)

LH

LH

ML

ML

ML

ML

(N/A)

(N/A)

MM

MM

MM

MM

MH

MH

(N/A)

(N/A)

HL

HL

MH

MH

HM

HM

(N/A)

(N/A)

HH

HH

HL

HL

(N/A)

(N/A)

HM

HM

(N/A)

(N/A)

LL/HH

LL

(N/A)

(N/A)

(N/A)

HH

Figure 3. Typical Outputs with FB Connected to a Zero-Skewed Output