HT46R652 datasheet(20/47 Pages) HOLTEK

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HT46R652

Rev. 1.00

December 19, 2006

To enable a counting operation, the Timer ON bit, T0ON

or T1ON should be set to 1. In the pulse width measure-

ment mode, the T0ON/T1ON is automatically cleared

after the measurement cycle is completed. But in the

other two modes, the T0ON/T1ON can only be reset by

instructions. The overflow of the Timer/Event Counter

0/1 is one of the wake-up sources and can also be used

to drive the PFD (Programmable Frequency Divider)

output on pin PA3, a function which is selected by a

configuration option. If PA3 is setup as a PFD output,

there are two types of selections. One is to use PFD0 as

the PFD output, the other is to use PFD1 as the PFD

output. PFD0 and PFD1 are the timer overflow signals

of the Timer/Event Counter 0 and Timer/Event Counter

1 respectively. No matter what the operation mode is,

writinga0to ET0I or ET1I disables the related interrupt

service. When the PFD function is selected, executing a

²SET [PA].3² instruction will enable the PFD output and

executing a

²CLR [PA].3² instruction will disable the

PFD output.

In cases where the timer/event counter is turned off,

writing data to the timer/event counter preload register

will also reload the new data into the timer/event coun-

ter. But if the timer/event counter is turned on, data writ-

ten to the timer/event counter will only be stored in the

timer/event counter preload register. The timer/event

counter will continue with its normal operation until an

overflow occurs.

When the timer/event counter is read, the clock is

blocked to avoid errors, which may result in a counting

error and should therefore be taken into account by the

programmer. It is strongly recommended to load a de-

sired value into the timer registers first before turning on

the related timer/event counter, for proper operation

since the initial value of the timer registers is unknown.

Due to the timer/event counter scheme, the program-

mer should pay special attention with instructions to en-

able then disable the timer for the first time, whenever

there is a need to use the timer/event counter function,

to avoid unpredictable results. After this procedure, the

timer/event function can be operated normally.

Bits 0~2 of TMR0C can be used to define the

pre-scaling stages of the internal clock sources of the

timer/event counter. The overflow signal of the

timer/event counter can be used to generate the PFD

signal. The timer prescaler is also used as the the PWM

counter.

Input/Output Ports

There are 32 bidirectional input/output lines in the

microcontroller, divided among several ports labeled as

PA, PB, PC and PD. All of these I/O ports can be used

for input and output operations. For input operation,

these ports are non-latching, that is, the inputs must be

ready at the T2 rising edge of instruction

²MOV A,[m]².

For output operations, all the data is latched and re-

mains unchanged until the output latch is rewritten.

Each port has has its own Port Control Register, known as

PAC, PBC, PCC and PDC to control the input/output con-

figuration. With this control register, a CMOS output or

Schmitt Trigger input with or without pull-high resistor

structures can be reconfigured dynamically under soft-

ware control. To function as an input, the corresponding bit

of the control register must contain a

²1². The input source

also depends on the control register. If the control register

bit is

²1², the input will read the pad state. If the control reg-

ister bit is

²0², the contents of the latches will move to the

internal bus. The latter is possible in the

²read-mod -

ify-write

² instruction.

After a device reset, as the Port Control Registers will be

set high, the input/output lines will be setup as inputs,

and will be at a high level or in a floating state, depend-

ing on the pull-high configuration options. Each bit of

these input/output latches can be set or cleared by the

²SET [m].i² and ²CLR [m].i² instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations (bit-opera-

tion), and then write the results back to the latches or the

accumulator.

Each line of port A has the capability of waking-up the

device. Each I/O port has pull-high options. Once the

pull-high option is selected, the I/O port has a pull-high

resistor. It should be noted that a non-pull-high I/O port

operating in an input mode will be in a floating condition.

Pin PA3 is pin-shared with the PFD signal. If the PFD

configuration option is selected, the output signal for

PA3, if it setup as an output, will be the PFD signal gen-

erated by the timer/event counter overflow signal. If

setup as an input the PA3 will always retain its input

function. Once the PFD configuration option is selected,

the PFD output signal can be controlled by the PA3 data

²1² to the PA3 data register will enable

the PFD output function while writing a

²0² will force the

PA3 pin to remain in a low condition. The I/O functions of

the PA3 pin are shown in the table.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

Pins PA0, PA1, PA3, PA5, PA6, PA4 and PA7 are

pin-shared with the BZ, BZ, PFD, INT0, INT1, TMR0

and TMR1 pins respectively.

The PA0 and PA1 pins are pin-shared with the BZ and

BZ signal, respectively. If the BZ/BZ option is selected,

the output signal in the output mode of PA0/PA1 will be

the buzzer signal, which is generated by the multi-func-

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