PM7367 datasheet(268/323 Pages) PMC

268 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

254

FBTBEN:

As a master, the GPIC does not generate fast back-to-back cycles to different

devices. This bit is forced low.

The upper 16-bits make up the PCI Status field. The status field tracks the status

of PCI bus related events. Reads to this register behave normally. Writes are

slightly different in that bits can be reset, but not set. A bit is reset whenever the

FBTBE:

The FBTBE bit is hardwired to one to indicate the GPIC supports fast back-

to-back transactions with other targets.

DPR:

The Data Parity Reported (DPR) bit is set high if the GPIC is an initiator and

asserts or detects a parity error on the PERRB signal while the PERREN bit

is set in the Command register. The DPR bit is cleared by the PCI Host.

DVSLT[1:0]:

The Device Select Timing (DEVSLT) bits specify the allowable timings for the

assertion of DEVSELB by the GPIC as a target. These are encoded as 00B

for fast, 01B for medium, 10B for slow and 11B is not used. The GPIC allows

for medium timing.

TABT:

The Target Abort (TABT) bit is set high by the GPIC when as a target, it

terminates a transaction with a target abort. The TABT bit is cleared by the

PCI Host.

RTABT:

The Received Target Abort (RTABT) bit is set high by the GPIC when as an

initiator, its transaction is terminated by a target abort. The RTABT bit is

cleared by the PCI Host.

MABT:

The Master Abort (MABT) bit is set high by the GPIC when as an initiator, its

transaction is terminated by a master abort and a special cycle was not in

progress. The MABT bit is cleared by the PCI Host.

SERR:

The System Error (SERR) bit is set high whenever the GPIC asserts the

SERRB output. The SERR bit is cleared by the PCI Host.

PM7367 датащи(PDF) 268 Page - PMC-Sierra, Inc