PM7367 datasheet(264/323 Pages) PMC

264 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

250

PCI CONFIGURATION REGISTER DESCRIPTION

PCI configuration registers are implemented by the PCI Interface. These

registers can only be accessed when the PCI Interface is a target and a

configuration cycle is in progress as indicated using the IDSEL input.

Notes on PCI Configuration Register Bits:

1. Writing values into unused register bits has no effect. However, to ensure

software compatibility with future, feature-enhanced versions of the product,

unused register bits must be written with logic zero. Reading back unused

bits can produce either a logic one or a logic zero; hence unused register bits

should be masked off by software when read.

2. Except where noted, all configuration bits that can be written into can also be

read back. This allows the processor controlling the FREEDM-32P32 to

determine the programming state of the block.

3. Writable PCI configuration register bits are cleared to logic zero upon reset

unless otherwise noted.

4. Writing into read-only PCI configuration register bit locations does not affect

FREEDM-32P32 operation unless otherwise noted.

5. Certain register bits are reserved. These bits are associated with megacell

functions that are unused in this application. To ensure that the FREEDM-

32P32 operates as intended, reserved register bits must only be written with

their default values. Similarly, writing to reserved registers should be

avoided.

10.1 PCI Configuration Registers

PCI configuration registers can only be accessed by the PCI host. For each

offset.

PM7367 датащи(PDF) 264 Page - PMC-Sierra, Inc