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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM69 датащи(PDF) 9 Page - Texas Instruments |
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AM69 датащи(HTML) 9 Page - Texas Instruments |
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9 / 312 page  5 Terminal Configuration and Functions 5.1 Pin Diagrams Note The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Figure 5-1 shows the ball locations for the 1414-ball flip chip ball grid array (FCBGA) package to quickly locate signal names and ball grid numbering. This figure is used in conjuction with Table 5-1 through Section 5.4 (Pin Attributes table and all Signal Descriptions tables, including the Pin Connectivity Requirements table). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV Not to scale VSS VSS DDR1 _DQS3P DDR1 _DQS3N VSS DDR1_DQ28 VSS DDR1 _DQS2P DDR1 _DQS2N VSS DDR1_CKN VSS DDR1 _DQS1P DDR1 _DQS1N VSS DDR1 _DQS0P DDR1 _DQS0N DDR3 _DQS0P DDR3 _DQS0N VSS DDR3 _DQS1P DDR3 _DQS1N VSS DDR3_CKP VSS DDR3 _DQS2P DDR3 _DQS2N VSS DDR3 _DQS3P DDR3 _DQS3N VDDS_DDR MCU_OSPI0 _CSn0 MCU_OSPI0 _CSn1 VSS MCU _RGMII1 _RD0 MCU_MDIO0 _MDC VSS VDDS_DDR DDR1_DQ24 DDR1_DQ25 DDR1_DQ26 DDR1_DQ27 VSS DDR1_DQ22 DDR1_DQ21 VSS DDR1_CKP VSS DDR1_CA2 VSS DDR1_DQ9 DDR1_DQ8 VSS DDR1_DQ6 DDR3_DQ1 VSS DDR3_DQ14 DDR3_DQ13 VSS DDR3_CA1 VSS DDR3_CKN VSS DDR3_DQ17 DDR3_DQ16 VSS DDR3_DQ30 VSS MCU_OSPI0 _D1 MCU_OSPI0 _D0 MCU_OSPI0 _CSn2 MCU_MDIO0 _MDIO MCU _RGMII1 _RD1 MCU _RGMII1 _RXC VSS DDR1_DM3 VSS DDR1_DQ31 VSS DDR1_DQ29 DDR1_DQ30 DDR1_DQ23 VSS DDR1_DQ20 DDR1_CKE1 DDR1_CA3 DDR1_CA1 DDR1_DQ10 VSS DDR1_DM1 DDR1_DQ5 VSS VSS DDR3_DQ2 DDR3_DQ15 VSS DDR3_DQ12 DDR3 _RESETn DDR3_CA3 DDR3_CKE0 DDR3_DQ18 VSS DDR3_DM2 DDR3_DQ29 VSS MCU_OSPI1 _LBCLKO MCU_OSPI0 _CSn3 MCU_OSPI0 _D2 MCU_OSPI0 _DQS MCU_OSPI0 _D3 MCU _RGMII1 _RD2 MCU _RGMII1 _RX_CTL MCU _RGMII1 _TX_CTL DDR2 _DQS3N DDR2_DQ25 VSS DDR2_DQ31 DDR2_DM3 VSS VSS DDR1_DM2 DDR1_DQ19 VSS DDR1_CKE0 DDR1_CA4 DDR1_DQ11 DDR1_DQ15 VSS DDR1_DQ4 DDR1_DQ7 DDR3_DQ0 DDR3_DQ3 VSS DDR3_DM1 DDR3_DQ11 VSS DDR3_CA2 DDR3_CA0 DDR3_DQ19 DDR3_DQ23 VSS DDR3_DQ28 DDR3_DQ31 MCU_OSPI1 _D1 MCU_OSPI0 _LBCLKO MCU_OSPI0 _D4 MCU_OSPI0 _D5 VSS MCU _RGMII1 _RD3 MCU _RGMII1 _TD0 MCU _RGMII1 _TD1 DDR2 _DQS3P VSS DDR2_DQ28 DDR2_DQ24 VSS DDR2_DQ30 DDR2_DQ29 DDR1_DQ16 VSS DDR1_CA5 DDR1_CSn0 _0 VSS VSS DDR1_DQ14 DDR1_DQ3 VSS DDR1_DM0 DDR3_DM0 VSS DDR3_DQ5 DDR3_DQ8 VSS DDR3_CA4 DDR3_CSn1 _1 VSS VSS DDR3_DQ22 DDR3_DQ27 VSS DDR3_DM3 VSS MCU_OSPI0 _CLK MCU_OSPI0 _D7 MCU_OSPI0 _D6 MCU_OSPI1 _D0 MCU _RGMII1 _TXC MCU _RGMII1 _TD2 MCU _RGMII1 _TD3 VSS DDR2_DQ23 DDR2_DQ16 VSS DDR2_DQ27 DDR2_DQ26 VSS VSS DDR1_DQ18 DDR1_CSn1 _0 VSS DDR1_CA0 DDR1_DQ12 VSS DDR1_DQ2 DDR1_DQ0 VSS DDR3_CAL0 DDR3_DQ7 DDR3_DQ4 VSS DDR3_DQ10 DDR3_CA5 VSS DDR3_CSn1 _0 DDR3_DQ20 VSS DDR3_DQ26 DDR3_DQ24 VSS MCU_OSPI1 _DQS MCU_OSPI1 _CLK MCU_OSPI1 _D3 RESET _REQz EMU0 MCU_RESETS TATz MCU_SPI0 _CS0 MCU_MCAN0 _RX DDR2 _DQS2N DDR2_DQ20 VSS DDR2_DM2 DDR2_DQ22 VSS DDR2_DQ17 DDR1_RET DDR1_DQ17 DDR1 _RESETn DDR1_CSn0 _1 DDR1_CSn1 _1 DDR1_DQ13 DDR1_CAL0 VSS DDR1_DQ1 VSS DDR3_DQ6 VSS DDR3_DQ9 DDR3_CSn0 _0 DDR3_CKE1 DDR3_CSn0 _1 DDR3_DQ21 DDR3_RET VSS DDR3_DQ25 MCU_OSPI1 _D2 MCU_OSPI1 _CSn0 MCU_OSPI1 _CSn1 MCU_I2C0 _SDA TCK MCU _RESETz TRSTn MCU_SPI0 _CLK DDR2 _DQS2P VSS DDR2_DQ21 DDR2_DQ19 VSS DDR2_DQ18 VSS VSS VDDS_DDR VSS VDDS_DDR VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDD_CPU VSS VDD_CPU VSS VDDSHV1 _MCU VSS VDDSHV2 _MCU VSS VDDSHV0 _MCU VSS VSS EMU1 WKUP _GPIO0_4 MCU_SPI0 _D0 WKUP _GPIO0_14 WKUP _GPIO0_0 VSS DDR2_CKE1 DDR2_CSn0 _0 VSS DDR2 _RESETn DDR2_CSn0 _1 DDR2_CSn1 _0 VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDD_CPU VSS VDD_CPU VSS VDDSHV1 _MCU VSS VDDSHV2 _MCU VSS VDDSHV0 _MCU VSS VMON3_IR _VEXT1P8 VSS WKUP _GPIO0_1 WKUP _GPIO0_2 WKUP _GPIO0_3 WKUP _GPIO0_12 MCU_SPI0 _D1 DDR2_CKN VSS DDR2_CA0 DDR2_CA4 DDR2_CA2 VSS DDR2_CSn1 _1 VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VSS VDD_CPU VSS VDD_CPU VSS VDDSHV1 _MCU VSS VDDSHV2 _MCU VMON1_ER _VSYS VDDSHV0 _MCU VDDA_WKUP MCU_PORz MCU_MCAN0 _TX WKUP _UART0 _TXD WKUP _UART0 _RXD WKUP _GPIO0_5 WKUP _GPIO0_15 WKUP _GPIO0_13 VSS DDR2_CKP DDR2_CA1 DDR2_CA3 VSS DDR2_CKE0 DDR2_CA5 DDR2_RET VSS VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR VDDS_DDR _C1 VDDS_DDR VDDS_DDR _C3 VDDS_DDR VSS VDD_CPU VSS VDD_CPU VSS VDD_MCU CAP_VDDS1 _MCU CAP_VDDS2 _MCU CAP_VDDS0 _MCU VDD_MCU _WAKE1 VPP_MCU VSS VDDA_WKUP WKUP _GPIO0_10 WKUP _GPIO0_9 WKUP _GPIO0_8 WKUP _GPIO0_7 WKUP _GPIO0_6 PMIC _POWER _EN1 DDR2 _DQS1N VSS DDR2_DQ15 DDR2_DQ14 VSS DDR2_DM1 DDR2_DQ12 VSS VDDS_DDR VDDS_DDR _C2 VDD_CORE VDDA _TEMP1 VDD_CORE VDDA_0P8 _PLL_DDR1 VDD_CORE VSS VDD_CORE VDDA_0P8 _PLL_DDR3 VDD_CORE VSS VDDAR_CPU VSS VDD_MCU VSS VDD_MCU VDDA_MCU _TEMP VDDAR_MCU VDDA_MCU _PLLGRP0 VSS VSS VDDA_ADC0 VSS WKUP _GPIO0_49 WKUP _GPIO0_67 MCU_I2C0 _SCL WKUP _GPIO0_57 WKUP _GPIO0_56 WKUP _GPIO0_11 DDR2 _DQS1P DDR2_DQ8 VSS DDR2_DQ9 DDR2_DQ13 VSS VDDS_DDR VSS VDDS_DDR VDDA_0P8 _PLL_DDR2 VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CPU VSS VDD_CPU VDDAR_CPU VDDAR_MCU VSS VDD_MCU VMON2_IR _VCPU VDDA_POR _WKUP VDDA_OSC1 VDDA_ADC1 VSS VSS WKUP_I2C0 _SCL WKUP _GPIO0_66 WKUP_I2C0 _SDA MCU _SAFETY _ERRORn OSC1_XO VSS VSS DDR2_DQ10 DDR2_DQ11 VSS DDR2_DQ5 DDR2_DQ4 VSS VSS VDDS_DDR VSS VDD_CORE VDDA _PLLGRP7 VDDA _PLLGRP8 VSS VDD_CORE VSS VDD_CORE VSS VDD_CPU VSS VDD_MCU VSS VDD_MCU VSS VDD_MCU VMON4_IR _VEXT1P8 CAP_VDDS5 VSS VDDSHV5 VSS PORz MCU_ADC0 _AIN4 VSS MCU_ADC0 _AIN0 VSS OSC1_XI DDR2 _DQS0N VSS DDR2_DQ2 DDR2_DQ3 VSS DDR2_DQ1 DDR2_DQ7 VDDS_DDR VSS VDDS_DDR VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CPU VDDA _PLLGRP6 VDD_CPU VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VMON5_IR _VEXT3P3 VDDSHV5 VDDSHV5 VSS MCU_ADC0 _AIN6 VSS MCU_ADC0 _REFP VSS MCU_ADC0 _AIN5 VSS DDR2 _DQS0P DDR2_DM0 VSS DDR2_DQ0 DDR2_DQ6 VSS VSS VDDS_DDR VDDS_DDR _C0 VDD_CORE VSS VDD_CORE VSS VDDAR_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDDAR _CORE VSS VDD_CORE VSS CAP_VDDS2 VDDSHV2 VSS VDDSHV2 VSS MCU_ADC0 _AIN2 VSS MCU_ADC0 _AIN3 VSS WKUP_OSC0 _XI DDR0 _DQS0P DDR0_DQ0 VSS DDR0_DQ1 DDR0_DQ6 VSS DDR2_CAL0 VDDS_DDR VSS VDDS_DDR VDDA_0P8 _PLL_DDR0 VDD_CORE VSS VDD_CPU VSS VDDAR_CPU VSS VDD_CPU VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDD_WAKE0 VSS VDDSHV2 VSS MCU_ADC1 _AIN6 VSS MCU_ADC0 _REFN VSS WKUP_OSC0 _XO VSS DDR0 _DQS0N VSS DDR0_DM0 DDR0_DQ4 VSS DDR0_DQ7 DDR0_DQ5 VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VDDA _PLLGRP5 VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CORE VSS VDD_CORE VSS CAP_VDDS0 VDDSHV0 VSS VDDSHV0 VSS MCU_ADC1 _AIN2 VSS MCU_ADC0 _AIN1 VSS MCU_ADC0 _AIN7 VSS DDR0_DQ11 DDR0_DQ9 VSS DDR0_DQ3 DDR0_DQ2 VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDDAR_CPU VSS VDD_CPU VDDAR_CPU VDD_CPU VDDA _TEMP2 VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDSHV0 VDD_CORE MCU_ADC1 _AIN5 VSS MCU_ADC1 _REFN VSS MCU_ADC1 _AIN3 VSS DDR0 _DQS1N DDR0_DQ8 VSS DDR0_DQ13 DDR0_DQ14 VSS VSS VDD_CPU VSS VDDAR_CPU VSS VDD_CPU VSS VDDAR_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CORE VDDA _PLLGRP9 VDDA _TEMP0 VDDA _PLLGRP1 VDD_CORE VSS VDD_CORE VSS VSS MCU_ADC1 _AIN1 VSS MCU_ADC1 _AIN7 VSS MCU_ADC1 _AIN0 DDR0 _DQS1P VSS DDR0_DQ10 DDR0_DM1 VSS DDR0_DQ12 DDR0_DQ15 VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VDDA _PLLGRP12 VDD_CORE VSS VDD_CORE VDDA _PLLGRP0 VDD_CORE VSS VDD_CORE VPP_CORE MMC1_DAT2 MMC1_DAT0 VSS MCU_ADC1 _REFP VSS MCU_ADC1 _AIN4 VSS VSS DDR0_CKN DDR0_CA4 DDR0_CA2 VSS DDR0_CKE0 DDR0_CSn1 _0 VSS VDD_CPU VSS VDD_CPU VSS VDDAR_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CORE VDDA _PLLGRP13 VDDAR _CORE VSS VDD_CORE VSS VDD_CORE VSS VSS MMC1_DAT1 VSS MMC1_CMD VSS MMC1_CLK DDR0_CKP VSS DDR0_CA5 DDR0_CA3 DDR0_CA1 VSS DDR0_CSn0 _1 DDR0_RET VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDDAR_CPU VSS VDDAR_CPU VSS VDDAR_CPU VSS VDD_CPU VSS VDDAR _CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS MCASP1 _AXR1 MCAN2_TX MCASP1 _ACLKX MCASP0 _AXR8 MCASP2 _AXR0 MCASP1 _AXR2 MMC1_DAT3 VSS DDR0_CA0 DDR0_CKE1 VSS DDR0 _RESETn DDR0_CSn1 _1 DDR0_CSn0 _0 VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VDDA _TEMP4 VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS MCASP1 _AFSX MCASP0 _AXR12 VSS ECAP0_IN _APWM_OUT MCASP2 _ACLKX MCASP1 _AXR0 DDR0 _DQS2N VSS DDR0_DQ22 DDR0_DQ23 VSS DDR0_DQ20 DDR0_DQ17 DDR0_CAL0 VDDA_0P8 _DLL_MMC0 VDD_CPU VSS VDDAR_CPU VDDA _TEMP3 VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CPU VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE MCAN16_RX MCASP0 _AXR15 MCASP0 _AXR7 MCASP2 _AXR1 MCASP2 _AFSX MCAN0_RX DDR0 _DQS2P DDR0_DQ16 VSS DDR0_DQ21 DDR0_DQ19 VSS VSS VDDS_MMC0 VSS VDD_CPU VSS VDD_CORE VSS VDDAR _CORE VSS VDD_CORE VDDAR _CORE VDD_CORE VSS VDDAR _CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS MCAN13_TX MCASP0 _AXR14 MCASP0 _AXR11 MCASP0 _AXR6 MCASP0 _AXR0 MCAN0_TX VSS DDR0_DM2 DDR0_DQ18 VSS DDR0_DQ24 DDR0_DQ31 VSS VDDS_MMC0 VSS VDDS_MMC0 VDDAR _CORE VDD_CORE VDDA _PLLGRP2 VDD_CORE VSS VDD_CORE VDDA_0P8 _SERDES _C4 VDD_CORE VSS VDD_CORE VDDA_0P8 _SERDES _C2 VDD_CORE VDDA _PLLGRP10 VDD_CORE VSS VDD_CORE VSS VDDAR _CORE VSS VDD_CORE VSS VDD_CORE MCAN14_TX MCAN15_TX MCASP0 _AXR9 MCAN12_TX MCASP0 _AXR1 MCASP0 _AXR5 DDR0 _DQS3N VSS DDR0_DQ25 DDR0_DQ27 VSS DDR0_DQ29 DDR0_DQ30 VSS VDDS_MMC0 VSS VDDA_0P8 _UFS VDDA_0P8 _SERDES _C0_1 VDDA_0P8 _SERDES _C0_1 VSS VDDA_0P8 _SERDES _C0_1 VDDA_0P8 _SERDES _C0_1 VDDA_1P8 _SERDES4 VDDA_0P8 _SERDES _C4 VSS VDDA_0P8 _SERDES _C2 VDDA_1P8 _SERDES2 VSS VSS VDDA_1P8 _DSITX VDDA_1P8 _DSITX VSS VDDA_1P8 _CSIRX0_1 VDDA_1P8 _CSIRX0_1 VDDA_1P8 _CSIRX2 VSS VDD_CORE VSS MCAN13_RX MCAN16_TX VSS MCASP0 _AXR10 MCAN2_RX MCAN1_RX DDR0 _DQS3P DDR0_DQ26 VSS DDR0_DQ28 DDR0_DM3 VSS MMC0 _CALPAD VSS VSS VDDA_1P8 _UFS VSS VDDA_0P8 _SERDES0 _1 VDDA_1P8 _SERDES0 _1 VDDA_1P8 _SERDES0 _1 VDDA_0P8 _SERDES0 _1 VSS VDDA_0P8 _SERDES4 VDDA_0P8 _SERDES4 VDDA_3P3 _USB VDDA_0P8 _SERDES2 VDDA_0P8 _SERDES2 VSS VDDA_1P8 _SERDES2 _4 VDDA_0P8 _DSITX VDDA_0P8 _DSITX_C VDDA_0P8 _CSIRX0_1 VSS VDDA_0P8 _CSIRX2 VDDA_1P8 _CSIRX2 VDD_CORE VSS EXT _REFCLK1 MCAN12_RX PMIC _WAKE0n MCAN15_RX MCASP0 _AXR13 MCAN1_TX MCASP0 _AXR3 VDDS_DDR MMC0_DAT7 MMC0_DS MMC0_CLK MMC0_DAT3 MMC0_DAT4 MMC0_DAT2 MMC0_DAT0 VSS VSS VSS VDDA_0P8 _SERDES0 _1 VDDA_0P8 _SERDES0 _1 VSS VSS VSS VSS VSS VDDA_0P8 _USB VDDA_1P8 _USB VSS VSS VSS VSS VDDA_0P8 _CSIRX0_1 VSS VSS VSS VSS MCASP0 _AXR2 MCASP0 _AXR4 MCASP0 _ACLKX MCAN14_RX GPIO0_12 MCASP0 _AFSX VSS UFS0_TX _DN0 UFS0_TX _DP0 VSS MMC0_DAT6 MMC0_DAT1 MMC0_DAT5 MMC0_CMD SERDES1 _REXT VSS VSS VSS VSS VSS VSS VSS VSS VSS SERDES2 _REXT VSS DSI1 _TXRCALIB VSS CSI1 _RXRCALIB VSS VSS GPIO0_11 MCASP1 _AXR3 MCASP1 _AXR4 TDO TMS TDI RESETSTA Tz UFS0_RX _DN1 UFS0_RX _DP1 VSS UFS0_RX _DN0 UFS0_RX _DP0 VSS UFS0_REF _CLK UFS0_RSTn VSS VSS VSS VSS SERDES4 _REXT VSS VSS DSI0 _TXRCALIB VSS VSS CSI0 _RXRCALIB VSS CSI2 _RXRCALIB VSS SOC _SAFETY _ERRORn SPI0_D0 SPI0_D1 SPI0_CS0 VSS VSS UFS0_TX _DN1 UFS0_TX _DP1 VSS PCIE _REFCLK2 _N_OUT PCIE _REFCLK2 _P_OUT VSS PCIE _REFCLK1 _N_OUT PCIE _REFCLK1 _P_OUT VSS SERDES0 _REXT VSS VSS USB0_VBUS VSS USB0_ID USB0 _RCALIB VSS VSS DSI0_TXP3 DSI0_TXN3 VSS DSI1_TXP1 DSI1_TXN1 VSS CSI0 _RXCLKP CSI0 _RXCLKN VSS CSI2 _RXCLKN CSI2 _RXCLKP VSS EXTINTn I2C0_SCL TIMER_IO1 SPI0_CLK SERDES1 _TX3_N SERDES1 _TX3_P VSS PCIE _REFCLK0 _N_OUT PCIE _REFCLK0 _P_OUT VSS PCIE _REFCLK3 _N_OUT PCIE _REFCLK3 _P_OUT VSS SERDES0 _TX1_N SERDES0 _TX1_P VSS SERDES4 _TX0_N SERDES4 _TX0_P VSS USB0_DM USB0_DP VSS SERDES2 _TX3_N SERDES2 _TX3_P VSS DP0_AUXN DP0_AUXP VSS DSI0 _TXCLKP DSI0 _TXCLKN VSS DSI1 _TXCLKP DSI1 _TXCLKN VSS CSI1 _RXCLKP CSI1 _RXCLKN VSS CSI2_RXP2 CSI2_RXN2 VSS I2C0_SDA SPI0_CS1 VSS SERDES1 _TX2_N SERDES1 _TX2_P VSS SERDES1 _TX1_N SERDES1 _TX1_P VSS SERDES0 _RX0_N SERDES0 _RX0_P VSS SERDES0 _RX2_N SERDES0 _RX2_P VSS SERDES4 _RX0_N SERDES4 _RX0_P VSS SERDES4 _RX2_N SERDES4 _RX2_P VSS SERDES2 _TX2_N SERDES2 _TX2_P VSS SERDES2 _TX1_N SERDES2 _TX1_P VSS DSI0_TXP2 DSI0_TXN2 VSS CSI0_RXP3 CSI0_RXN3 VSS CSI1_RXP2 CSI1_RXN2 VSS CSI2_RXP0 CSI2_RXN0 VSS TIMER_IO0 SERDES1 _RX3_N SERDES1 _RX3_P VSS SERDES1 _RX1_N SERDES1 _RX1_P VSS SERDES0 _TX0_N SERDES0 _TX0_P VSS SERDES0 _RX1_N SERDES0 _RX1_P VSS SERDES4 _TX1_N SERDES4 _TX1_P VSS SERDES4 _TX2_N SERDES4 _TX2_P VSS SERDES2 _RX3_N SERDES2 _RX3_P VSS SERDES2 _RX1_N SERDES2 _RX1_P VSS DSI0_TXP1 DSI0_TXN1 VSS DSI1_TXP0 DSI1_TXN0 VSS CSI0_RXP1 CSI0_RXN1 VSS CSI1_RXP0 CSI1_RXN0 VSS CSI2_RXP1 CSI2_RXN1 VSS SERDES1 _RX2_N SERDES1 _RX2_P VSS SERDES1 _RX0_N SERDES1 _RX0_P VSS SERDES0 _REFCLK_P SERDES0 _REFCLK_N VSS SERDES0 _RX3_N SERDES0 _RX3_P VSS SERDES4 _RX1_N SERDES4 _RX1_P VSS SERDES4 _RX3_N SERDES4 _RX3_P VSS SERDES2 _RX2_N SERDES2 _RX2_P VSS SERDES2 _RX0_N SERDES2 _RX0_P VSS DSI0_TXP0 DSI0_TXN0 VSS DSI1_TXP3 DSI1_TXN3 VSS CSI0_RXP0 CSI0_RXN0 VSS CSI1_RXP1 CSI1_RXN1 VSS VSS VSS VSS SERDES1 _REFCLK_N SERDES1 _REFCLK_P VSS SERDES1 _TX0_N SERDES1 _TX0_P VSS SERDES0 _TX2_N SERDES0 _TX2_P VSS SERDES0 _TX3_N SERDES0 _TX3_P VSS SERDES4 _REFCLK_P SERDES4 _REFCLK_N VSS SERDES4 _TX3_N SERDES4 _TX3_P VSS SERDES2 _REFCLK_N SERDES2 _REFCLK_P VSS SERDES2 _TX0_N SERDES2 _TX0_P VSS DSI1_TXP2 DSI1_TXN2 VSS CSI0_RXP2 CSI0_RXN2 VSS CSI1_RXP3 CSI1_RXN3 VSS CSI2_RXP3 CSI2_RXN3 Figure 5-1. ALY FCBGA-N1414 Pin Diagram (Top View) www.ti.com AM69A, AM69 SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: AM69A AM69 |
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