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AM69 датащи(PDF) 1 Page - Texas Instruments

номер детали AM69
подробное описание детали  AM69x Processors, Silicon Revision 1.0
PDF  312 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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AM69 датащи(HTML) 1 Page - Texas Instruments

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AM69x Processors, Silicon Revision 1.0
1 Features
Processor cores:
• Up to eight 64-bit Arm® Cortex®-A72
microprocessor subsystem at up to 2GHz
– 2MB shared L2 cache per quad-core Cortex®-
A72 cluster
– 32KB L1 D-Cache and 48KB L1 I-Cache per
Cortex®-A72 core
• Up to Four Deep Learning Accelerators:
– Each with up to 8 Trillion Operations Per
Second (TOPS)
– Total of 32 Trillion Operations Per Second
(32TOPS)
• Dual-core Arm® Cortex®-R5F MCUs at up to
1.0GHz in General Compute partition with FFI
– 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB
L2 TCM
• Dual-core Arm® Cortex®-R5F MCUs at up to
1.0GHz to support Device Management
– 32K L1 D-Cache, 32K I-Cache, and 64K L2
TCM with SECDED ECC on all memories
• Up to two Vision Processing Accelerators (VPAC)
with Image Signal Processor (ISP) and multiple
vision assist accelerators
– 480MPixel/s ISP
– Support for up to 16-bit input RAW format
– Wide Dynamic Range (WDR), Lens Distortion
Correction (LDC), Vision Imaging Subsystem
(VISS), and Multi-Scalar (MSC) support
– Output color format : 8-bits, 12-bits, and YUV
4:2:2, YUV 4:2:0, RGB, HSV/HSL
• Multimedia:
– Display subsystem supports:
• Up to 4 displays
• Up to two DSI 4L TX (up to 2.5K)
• One eDP 4L
• One DPI 24-bit RGB parallel interface
• Safety features such as freeze frame
detection and MISR data check
– 3D Graphics Processing Unit
• IMG BXS-4-64, up to 800MHz
• 50GFLOPS, 4GTexels/s
• Support for APIs OpenGL ES 3.1, Vulkan
1.2
– Three CSI2.0 4L Camera Serial interface RX
(CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with
DPHY
• MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
• Support for 1,2,3, or 4 data lane mode up to
2.5Gbps
• ECC verification/correction with CRC check
+ ECC on RAM
• Virtual Channel support (up to 16)
• Ability to write stream data directly to DDR
via DMA
– Two Video Encoder/Decoder Modules
• Support for HEVC (H.265) Main profiles at
Level 5.1 High-tier
• Support for H.264 BaseLine/Main/High
Profiles at Level 5.2
• Support for up to 4K UHD resolution (3840 ×
2160) per module
• Each module supports 4K60 H.264/H.265
Encode/Decode (up to 480MP/s)
Memory subsystem:
• Up to 8MB of on-chip L3 RAM with ECC and
coherency
– ECC error protection
– Shared coherent cache
– Supports internal DMA engine
• Up to Four External Memory Interface (EMIF)
module with ECC
– Supports LPDDR4 memory types
– Supports speeds up to 4266MT/s
– Up to 4x32-b bus with inline ECC up to 68GB/s
• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected
by ECC
• AEC-Q100 qualified on part number variants
ending in Q1
Device security:
• Secure boot with secure run-time support
• Customer programmable root key, up to RSA-4K
or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC,
AES, SHA, RNG, DES and 3DES 
High speed serial interfaces:
• Integrated Ethernet switch supporting up to 8
external ports
– Two ports support 5Gb, 10Gb USXGMII or 5Gb
XFI
– All ports support 1Gb, 2.5Gb SGMII
– All ports can support QSGMII. A maximum of 2
QSGMII can be enabled and uses all 8 internal
lanes. 1 QSGMII interfaces uses 4 internal
lanes.
AM69A, AM69
SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.


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