HT45F0057 datasheet(37/88 Pages) HOLTEK

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HT45F0057

Induction Cooker Flash MCU

HT45F0057

Induction Cooker Flash MCU

Timer/Event Counter Registers – TMR0, TMR1, TMR2

The timer registers are special function registers located in the Special Purpose Data Memory and

is the place where the actual timer value is stored. The value in the timer registers increases by one

each time an internal clock pulse is received or an external transition occurs on the external timer

pin. The timer will count from the initial value loaded by the preload register to the full count of

FFH at which point the timer overflows and an internal interrupt signal is generated. Then the timer

value will be reset with the initial preload register value and continue counting.

Note that to achieve a maximum full range count of FFH, all the preload registers must first be

cleared to zero. It should be noted that after power-on, the preload registers will be in an unknown

condition. Note that if the Timer/Event Counter is in an OFF condition and data is written to its

preload register, this data will be immediately written into the actual counter. However, if the

counter is enabled and counting, any new data written into the preload data register during this

period will remain in the preload register and will only be written into the actual counter the next

time an overflow occurs.

Timer Control Registers – TMR0C, TMR1C, TMR2C

The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate

in several different modes, the options of which are determined by the contents of their respective

control register. The Timer Control Register is known as TMRnC. It is the Timer Control Register

together with its corresponding timer registers that control the full operation of the Timer/Event

Counter. Before the timer can be used, it is essential that the Timer Control Register is fully

programmed with the right data to ensure its correct operation, a process that is normally carried out

during program initialisation.

To choose which of the several modes the timer is to operate in, either in the timer mode, the event

counting mode, the pulse width capture mode or the PPG non-retriggered function mode 0, bits 7

and 6 of the Timer Control Register, which are known as the bit pair T0M1/T0M0 or T1M1/T1M0,

must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register

and known as TnON, provides the basic on/off control of the respective timer. Setting the bit high

allows the counter to run. Clearing the bit stops the counter. Bits 0~2 of the Timer Control Register

determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if

an external clock source is used. If the timer is in the event count or pulse width capture mode, the

active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register

TMR0C which is known as TMR0E.

8-bit Timer/Event Counter

Preload Register

8-bit Timer/Event

Counter (TMR0)

Pulse Width

Mesurement

Mode Control

TMR0ECS

T0M1

T0M0

T0ON

fT0

Data bus

Reload

Overflow to

Interrupt

T0M1

T0M0

TMR0E

MUX

TMR0

INT0

Note: INT0 is inverted or non-inverted de-bounce signal from INT pin or comparator 0 output

“C0VO” by software option.

8-bit Timer/Event Counter 0

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