HT45F0057 datasheet(52/88 Pages) HOLTEK

52 / 88 page

Rev. 1.00

5�

��to�e� �0� �01�

Rev. 1.00

��to�e� �0� �01�

HT45F0057

Induction Cooker Flash MCU

HT45F0057

Induction Cooker Flash MCU

Programmable Pulse Generator

The device provides a 9-bit PPG output channel. The PPG has a programmable period of 512×T,

where T is 1/fSYS for an output pulse width. The PPG pulse width could be limited with using pulse

width limiter timer.

The PPG detects a trigger input, and outputs a single pulse. The trigger source may come from

INT00 falling edge or software trigger bit, which can be configured by software. The PPG can

output an active low or active high pulse by setting the configuration option. The PPG output is

floating when VDD is between 0.6V and 1.2V, Reset occurs, and the PPG is inactive; an external pull-

high or pull-low resistor depended on polarity configuration option is need.

CP 1N

IN T

Pr el oad R eg is te r B

PPG T im er ( 9 bi t)

Re lo ad

PP G

Ou tp ut

Logi c

PP G Ti me r On / Of f

c on fi gu ra ti on

Da ta bus

Ov er fl ow

PPG M ode

C on tr ol

t ri gger e d ge c ont ro l

ri si ng or f al lg i ng se le ct io n

f PP G

f SY S

PP G st ar t st ar t SYN C op ti on

PPG a ct iv e (S yn c mo de)

PPG

st ar t

PPG

st op

PS T

CP 0P

CP 0N

PW L

C1 VO B

C0 VO

de- bounc e

Pr el oad R eg is te r A

RL BF = 0 , re l oad fr om A

RL BF = 1 , re l oad fr om B

( RL BF i s se t by C 1V O fa lli ng

edge i f C1 CT L= 0,

cl ear ed by s of tw ar e )

re lo ad c ont ro l

IN T0 0

PP GO UT

PP G_ st ar t

PP GO UT

one s hot

SET _T 1O N

IN H

PW L

DB C5 ~0

IN TS

PSPEN

RL BF

co nt ro l

CL R_ PR SE N

one s hot

No te : PR SE N wi ll be cl ear ed by th e

fa llin g e dge o f C2 VO B or C 3V OB

PR SEN

CL R_ PR SE N

PR SEN

c on tr ol

CP 2N

C2 VO

CP 1P

CP 2P

one s hot

C1 RL EN

Pu ls e Wi dt h Li mi t Ti me r

(P WL T)

f SY S / 2

Pu ls e Wi dt h Li mi t Ti me r

Pr el oad R eg is te r

Ov er fl ow

Re l oad

PW L

Re l oad

PW L

IN TI NV

tr i ger

del ay

f SY S

IN T0

VR 1

CM P0

CM P1

CM P2

VR 2

VR 3

AN 9

PP G

1. Fl oa ti ng f or re se t, i na ct iv e, a nd a c ondi ti on

0 .6 V< V DD< 1. 2V

2. Hi / Lo b y co nf i gur at io n op ti on f or a ct iv e

C2 VO IN V

IO FF

Ou tp ut

Logi c

IO FF

1. Fl oa ti ng f or re se t

2. Hi / Lo w hen PP G in ac ti ve / ac ti ve

C1 CT L

C2 VO B

PPG DL 5~ 0

tr i ger

m ode

TR GM OD

IN T0 S

.... .

C3 VO

CM P3

VR 4

C3 VO IN V

CP 0P

CP 3N

C3 VO B

D eboun ce

0. 5u s

De boun ce

0. 5u s

D ebounc e

0. 5u s

CM P3 D ebounc e E nabl e

(C on fi gur at i on)

CM P2 D ebounc e On

(C on fi gur at i on)

CM P1 D ebounc e On

(C on fi gur at i on)

CM P0 / 1/ 2

E nabl e

C onf i gur at io n

O PAO

C1 VO

PPG Block Diagram

The PPG module consists of one PPG timer, one PPG Mode Control and four comparators. The PPG

timer consists of one 9-bit up-counter timer, and two 9-bit preload data registers. The programmable

pulse generator PPG starts counting at the current contents in the preload register and ends at

“1FFH → 000H”. A “000H” data write to the PPGTA and PPGTB register yields a pulse width

512×T output. Once an overflow occurs, the counter is reloaded from the PPG timer counter preload

when the PPG timer overflow occurs.

HT45F0057 датащи(PDF) 52 Page - Holtek Semiconductor Inc

HT45F0057 датащи(HTML) 52 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

датащи скачать

ссылки URL