HT45F0057 datasheet(47/88 Pages) HOLTEK

47 / 88 page

Rev. 1.00

��to�e� �0� �01�

Rev. 1.00

4�

��to�e� �0� �01�

HT45F0057

Induction Cooker Flash MCU

HT45F0057

Induction Cooker Flash MCU

PCRH Register

Bit

Name

—

PCR9

PCR8

R/W

—

R/W

P�R

—

Bit 7~2

Unimplemented, read as “0”

Bit 1

PCR9: Internal analog input channel AN9 enable

0: Internal analog input channel AN9 disabled

1: Internal analog input channel AN9 enabled

Bit 0

PCR8: Define PA1 is A/D input or not

0: Not A/D input

1: A/D input, AN8

A/D Operation

The START bit in the ADCR register is used to start and reset the A/D converter. When the

microcontroller sets this bit from low to high and then low again, an analog to digital conversion

cycle will be initiated. When the START bit is brought from low to high but not low again, the

EOCB bit in the ADCR register will be set high and the analog to digital converter will be reset. It

is the START bit that is used to control the overall start operation of the internal analog to digital

converter.

The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process

is complete. This bit will be automatically set to zero by the microcontroller after a conversion

cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt

control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be

generated. This A/D internal interrupt signal will direct the program flow to the associated A/D

internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller

can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an

alternative method of detecting the end of an A/D conversion cycle.

The clock source for the A/D converter originates from the subdivided version of fSYS. The division

ratio value is determined by the ADCS1~ADCS0 bits in the ACSR register.

Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS1~ADCS0,

there are some limitations on the maximum A/D clock source speed that can be selected. As the

minimum value of permissible A/D clock period, tADCK, is 0.5 μs, care must be taken for system

clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a

frequency of 4MHz, the ADCS1~ADCS0 bits should not be set to “00”. Doing so will give A/D

clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D

conversion values. Refer to the following table for examples, where values marked with an asterisk

* show where, depending upon the device, special care must be taken, as the values may be less than

the specified minimum A/D Clock Period.

fSYS

A/D Clock Period(tADCK)

ADCS1~ADCS0=00

(fSYS/2)

ADCS1~ADCS0=01

(fSYS/8)

ADCS1~ADCS0=10

(fSYS/32)

ADCS1~ADCS0=11

1MHz

2μs

8μs

32μs

Undefined

�MHz

1μs

4μs

16μs

Undefined

4MHz

500ns

2μs

8μs

Undefined

8MHz

�50ns*

1μs

4μs

Undefined

A/D Clock Period Examples

HT45F0057 датащи(PDF) 47 Page - Holtek Semiconductor Inc

HT45F0057 датащи(HTML) 47 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

датащи скачать

ссылки URL