ADA4945-1ACPZ-R7 datasheet(51/57 Pages) AD

51 / 57 page

Data Sheet

ADA4945-1

analog.com

Rev. A

51 of 57

When more accurate control of the output common-mode level is required, it is recommended that an external

source, or resistor divider (10 kΩ or greater resistors), be used. The output common-mode offset listed in Table 2,

Table 5, and Table 8 assumes that the VOCM input is driven by a low impedance voltage source.

It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC. However, care must be

taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately

125 kΩ.

Disable Pin

The ADA4945-1 features a DISABLE pin that can be used to minimize the quiescent current consumed when the

device is not being used. DISABLE is asserted by applying a low logic level to the DISABLE pin. The logic level for the

DISABLE

pin is referenced to DGND. See Table 3, Table 6, and Table 9 for the threshold limits.

The DISABLE pin features an internal pull-up network that enables the amplifier for normal operation. The ADA4945-

1 DISABLE pin can be left floating (that is, no external connection is required) and does not require an external pullup

resistor to ensure normal on operation (see Figure 110). When the ADA4945-1 is disabled, the output is high

impedance. Note that the outputs are tied to the inputs through the feedback resistors and to the source using the

gain resistors. In addition, there are back to back diodes on the input pins that limit the differential voltage to 1.2 V.

Figure 110. DISABLE Pin Circuit

Driving a Capacitive Load

A purely capacitive load reacts with the bond wire and pin inductance of the ADA4945-1, resulting in high frequency

ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a resistor in

series with each output to buffer the load capacitance. The resistor and load capacitance form a first-order, low-pass

filter. Therefore, the resistor value must be as small as possible. In some cases, the ADCs require small series resistors

to be added on their inputs.

Figure 111 shows the capacitive load vs. the series resistance required to maintain a minimum 45° of phase margin.

The test circuit is shown in Figure 112.

DISABLE

AMPLIFIER

BIAS CURRENT

–VS

+VS

DGND

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