ADA4945-1ACPZ-R7 datasheet(45/57 Pages) AD

45 / 57 page

Data Sheet

ADA4945-1

analog.com

Rev. A

45 of 57

Figure 101. Differential Clamp Block Diagram

By applying a differential feedback signal in response to one or both outputs exceeding the clamp reference voltages,

both outputs are limited equally, even if only one output exceeds one of the clamp reference voltages. This feature

allows the ADA4945- 1 to maintain a constant output common-mode voltage even while clamping the differential

outputs, which enables a faster system recovery from a clamped condition.

In systems where output clamping is not desired, the upper output clamp can be disabled by connecting +VCLAMP to

+VS, and the lower output clamp can be disabled by connecting −VCLAMPto −VS. If one clamp is disabled (for example,

−VS= −VCLAMP = 0 V), the other can be remain active, and the output is limited when either or both outputs reaches the

active clamp reference.

An additional feature of the ADA4945-1 is the use of a resistor divider between the +VCLAMP and −VCLAMP pins, as shown

in Figure 99, to set the default potential on the VOCM pin when the pin is not externally driven. Because the +VCLAMP and

−VCLAMP pins are typically set to the maximum and minimum desired input voltage of the ADC (for example, +VREF and

−VREF), respectively, this resistor divider sets the output common-mode voltage of the ADA4945-1 at the midpoint of

the ADC input range by default. By contrast, most fully-differential amplifiers use a resistor divider between the

amplifier supply voltages to set the default output common-mode voltage, which may not be optimal for maximizing

ADC input range usage.

Power Modes

The ADA4945-1 implements two fully characterized active power modes (full power, low power) and a disable mode

to optimize system power and performance trade-offs. The transition time from disable mode to either of the active

power modes is fast (<2μs), allowing additional power savings by dynamically placing the ADA4945-1 in disable mode

when the output voltage is not needed (for example, between ADC samples in low data rate systems).

–OUT

+VCLAMP

UPPER

DIFFERENTIAL

CLAMP

iCLAMP (DIFF)

+OUT

–

500 mV

LOWER

DIFFERENTIAL

CLAMP

–VCLAMP

500 mV

iCLAMP (DIFF)

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