LTC2415-1IGN datasheet(31/40 Pages) LINER

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LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 29. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference

Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF)

VINDIF/VREFDIF

–0.5 –0.4–0.3–0.2–0.1 0

0.1 0.2 0.3 0.4 0.5

–3

–6

–9

–12

–15

VCC = 5V

REF+ = 5V

REF– = GND

VINCM = 0.5 • (IN

+ + IN–) = 2.5V

FO = GND

CREF = 10µF

TA = 25°C

RSOURCE = 1000Ω

RSOURCE = 500Ω

RSOURCE = 100Ω

2415 F29

tance is 1.43M

Ω. When FO is driven by an external

oscillator with a frequency fEOSC (external conversion

clock operation), the typical differential reference resis-

tance is 0.20 • 1012/fEOSCΩ and each ohm of source

resistance driving REF+ or REF– will result in

2.47 • 10–6 • fEOSCppm gain error. The effect of the source

resistance on the two reference pins is additive with

respect to this gain error. The typical +FS and –FS errors

for various combinations of source resistance seen by the

REF+ and REF– pins and external capacitance CREF

connected to these pins are shown in Figures 25, 26, 27

and 28.

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

When FO = LOW (internal oscillator and 60Hz notch), every

100

Ωof source resistance driving REF+ or REF– translates

into about 1.34ppm additional INL error. For the LTC2415,

when FO = HIGH (internal oscillator and 50Hz notch), every

100

Ωof source resistance driving REF+ or REF– translates

into about 1.1ppm additional INL error; and for the

LTC2415-1 operating with simultaneous 50Hz/60Hz re-

jection, every 100

Ω of source resistance leads to an

additional 1.22ppm of additional INL error. When FO is

driven by an external oscillator with a frequency fEOSC,

every 100

Ω of source resistance driving REF+ or REF–

translates into about 8.73 • 10–6 • fEOSCppm additional INL

error. Figure 26 shows the typical INL error due to the

source resistance driving the REF+ or REF– pins when

large CREF values are used. The effect of the source

resistance on the two reference pins is additive with

respect to this INL error. In general, matching of source

impedance for the REF+ and REF– pins does not help the

gain or the INL error. The user is thus advised to minimize

the combined source impedance driving the REF+ and

REF– pins rather than to try to match it.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

0.5%. Such a specification can also be easily achieved by

an external clock. When relatively stable resistors

(50ppm/

°C) are used for the external source impedance

seen by REF+ and REF–, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its

value over the entire temperature and voltage range). Even

for the most stringent applications a one-time calibration

operation may be sufficient.

In addition to the reference sampling charge, the reference

pins ESD protection diodes have a temperature dependent

leakage current. This leakage current, nominally 1nA

(

±10nA max), results in a small gain error. A 100Ω source

resistance will create a 0.05

µV typical and 0.5µV maxi-

mum full-scale error.

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