LTC2415-1IGN datasheet(12/40 Pages) LINER

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LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 2. LTC2415 State Transition Diagram

CONVERTER OPERATION

Converter Operation Cycle

The LTC2415/LTC2415-1 are low power, delta-sigma ana-

log-to-digital converters with an easy to use 3-wire serial

interface (see Figure 1). Their operation is made up of

three states. The converter operating cycle begins with the

conversion, followed by the sleep state and ends with the

data output (see Figure 2). The 3-wire interface consists of

serial data output (SDO), serial clock (SCK) and chip select

(CS).

is updated on the falling edge of SCK allowing the user to

reliably latch data on the rising edge of SCK (see Figure 3).

The data output state is concluded once 32 bits are read

out of the ADC or when CS is brought HIGH. The device

automatically initiates a new conversion and the cycle

repeats.

Through timing control of the CS and SCK pins, the

LTC2415/LTC2415-1 offer several flexible modes of op-

eration (internal or external SCK and free-running conver-

sion modes). These various modes do not require pro-

gramming configuration registers; moreover, they do not

disturb the cyclic operation described above. These modes

of operation are described in detail in the Serial Interface

Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonly implemented as a Sinc or Comb filter). For

high resolution, low frequency applications, this filter is

typically designed to reject line frequencies of 50Hz or

60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

system clock. The LTC2415/LTC2415-1 incorporate a

highly accurate on-chip oscillator. This eliminates the

need for external frequency setting components such as

crystals or oscillators. Clocked by the on-chip oscillator,

the LTC2415 achieves a minimum of 110dB rejection at

the line frequency (50Hz or 60Hz

±2%), while the

LTC2415-1 achieves a minimum of 87db rejection at 50Hz

±2% and 60Hz ±2% simultaneously.

Ease of Use

The LTC2415/LTC2415-1 data output has no latency,

filter settling delay or redundant data associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog voltages is easy.

CONVERT

SLEEP

DATA OUTPUT

2415 F02

TRUE

FALSE

CS = LOW

AND

SCK

Initially, the LTC2415/LTC2415-1 perform a conversion.

Once the conversion is complete, the device enters the

sleep state. While in this sleep state, power consumption

is reduced by an order of magnitude if CS is HIGH. The part

remains in the sleep state as long as CS is HIGH. The

conversion result is held indefinitely in a static shift

Once CS is pulled LOW, the device begins outputting the

conversion result. There is no latency in the conversion

result. The data output corresponds to the conversion just

performed. This result is shifted out on the serial data out

pin (SDO) under the control of the serial clock (SCK). Data

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