LTC2415-1IGN datasheet(24/40 Pages) LINER

24 / 40 page

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 14. Internal Serial Clock, Autostart Operation

SDO

Hi-Z

SCK

(INTERNAL)

VCC

GND

2415 F14

BIT 0

SIG

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

EOC

BIT 31

VCC

REF+

REF–

SCK

IN+

IN –

SDO

GND

214

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

2-WIRE

INTERFACE

µF

2.7V TO 5.5V

LTC2415/

LTC2415-1

CEXT

= 50Hz REJECTION (LTC2415)

= EXTERNAL OSCILLATOR

= 60Hz REJECTION (LTC2415)

= 50Hz/60Hz REJECTION (LTC2415-1)

VCC

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 14. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 15 and 16. Once the

voltage at CS falls below an internal threshold (

≈1.4V), the

device automatically begins outputting data. The data

output cycle begins on the first rising edge of SCK and

ends on the 32nd rising edge. Data is shifted out the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.

After the 32nd rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-

cations requiring periodic monitoring and ultralow power.

Figure 17 shows the average supply current as a function

of capacitance on CS.

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the autostart

mode, the analog voltage on the CS pin cannot be ob-

served without disturbing the converter operation using a

regular oscilloscope probe. When using this configura-

tion, it is important to minimize the external leakage

current at the CS pin by using a low leakage external

capacitor and properly cleaning the PCB surface.

The internal serial clock mode is selected every time the

voltage on the CS pin crosses an internal threshold volt-

age. An internal weak pull-up at the SCK pin is active while

CS is discharging; therefore, the internal serial clock

timing mode is automatically selected if SCK is floating. It

is important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

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