LTC2415-1IGN datasheet(29/40 Pages) LINER

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LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 22. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)

Figure 23. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)

Figure 24. Offset Error vs Common Mode Voltage

(VINCM = IN+ = IN–) and Input Source Resistance Imbalance

(

∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)

RSOURCE (Ω)

0 100 200 300 400 500 600 700 800 900 1000

2415 F22

300

240

180

120

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = 3.75V

IN– = 1.25V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

RSOURCE (Ω)

0 100 200 300 400 500 600 700 800 900 1000

2415 F23

–60

–120

–180

–240

–300

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = 1.25V

IN– = 3.75V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

VINCM (V)

0.5

1.5

2.5

3.5

4.5

2415 F24

120

100

–20

–40

–60

–80

–100

–120

FO = GND

TA = 25°C

RSOURCEIN– = 500Ω

CIN = 10µF

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = IN– = VINCM

∆RIN = +400Ω

∆RIN = +200Ω

∆RIN = +100Ω

∆RIN = 0Ω

∆RIN = –100Ω

∆RIN = –200Ω

∆RIN = –400Ω

used for the external source impedance seen by IN+ and

IN–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications, a one-time

calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (

±10nA max), results

in a small offset shift. A 100

Ω source resistance will create

a 0.1

µV typical and 1µV maximum offset voltage.

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