SC26C92 datasheet(22/31 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

ISR[7] – Input Port Change Status

This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,

IP2, or IP3 inputs and that event has been selected to cause an

interrupt by the programming of ACR[3:0]. The bit is cleared when

the CPU reads the IPCR.

ISR[6] – Channel B Change In Break

This bit, when set, indicates that the Channel B receiver has

detected the beginning or the end of a received break. It is reset

when the CPU issues a Channel B ‘reset break change interrupt’

command.

ISR[5] – RxB Interrupt

This bit indicates that the channel B receiver is interrupting

according to the fill level programmed by the MR0 and MR1

registers. This bit has a different meaning than the receiver

ready/full bit in the status register.

ISR[4] – TxB Interrupt

This bit indicates that the channel B transmitter is interrupting

according to the interrupt level programmed in the MR0[5:4] bits.

This bit has a different meaning than the Tx RDY bit in the status

ISR[3] – Counter Ready.

In the counter mode, this bit is set when the counter reaches

terminal count and is reset when the counter is stopped by a stop

counter command.

In the timer mode, this bit is set once each cycle of the generated

square wave (every other time that the counter/timer reaches zero

count). The bit is reset by a stop counter command. The command,

however, does not stop the counter/timer.

ISR[2] – Channel A Change in Break

This bit, when set, indicates that the Channel A receiver has

detected the beginning or the end of a received break. It is reset

when the CPU issues a Channel A ‘reset break change interrupt’

command.

ISR[1] – RxA Interrupt

This bit indicates that the channel A receiver is interrupting

according to the fill level programmed by the MR0 and MR1

registers. This bit has a different meaning than the receiver

ready/full bit in the status register.

ISR[0] – TxA Interrupt

This bit indicates that the channel A transmitter is interrupting

according to the interrupt level programmed in the MR0[5:4] bits.

This bit has a different meaning than the Tx RDY bit in the status

IMR – Interrupt Mask Register

The programming of this register selects which bits in the ISR

causes an interrupt output. If a bit in the ISR is a ‘1’ and the

corresponding bit in the IMR is also a ‘1’ the INTRN output will be

asserted. If the corresponding bit in the IMR is a zero, the state of

the bit in the ISR has no effect on the INTRN output. Note that the

IMR does not mask the programmable interrupt outputs OP3-OP7 or

the reading of the ISR.

CTPU and CTPL – Counter/Timer Registers

The CTPU and CTPL hold the eight MSBs and eight LSBs,

respectively, of the value to be used by the counter/timer in either

the counter or timer modes of operation. The minimum value which

may be loaded into the CTPU/CTPL registers is H‘0002’. Note that

these registers are write-only and cannot be read by the CPU.

In the timer mode, the C/T generates a square wave whose period is

twice the value (in C/T clock periods) of the CTPU and CTPL. The

waveform so generated is often used for a data clock. The formula

for calculating the divisor n to load to the CTPU and CTPL for a

particular 1X data clock is shown below.

counter clock frequency

16x2x baud rate desired

Often this division will result in a non-integer number; 26.3, for

example. One can only program integer numbers in a digital divider.

Therefore, 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability asynchronous mode

of operation.

If the value in CTPU and CTPL is changed, the current half-period

will not be affected, but subsequent half periods will be. The C/T will

not be running until it receives an initial ‘Start Counter’ command

(read at address A3-A0 = 1110). After this, while in timer mode, the

C/T will run continuously. Receipt of a start counter command (read

with A3-A0 = 1110) causes the counter to terminate the current

timing cycle and to begin a new cycle using the values in CTPU and

CTPL.

The counter ready status bit (ISR[3]) is set once each cycle of the

square wave. The bit is reset by a stop counter command (read

with A3-A0 = H’F’). The command however, does not stop the C/T.

The generated square wave is output on OP3 if it is programmed

to be the C/T output.

In the counter mode, the value C/T loaded into CTPU and CTPL by

the CPU is counted down to 0.. Counting begins upon receipt of a

start counter command. Upon reaching terminal count H‘0000’, the

counter ready interrupt bit (ISR[3]) is set. The counter continues

counting past the terminal count until stopped by the CPU. If OP3 is

programmed to be the output of the C/T, the output remains High

until terminal count is reached, at which time it goes Low. The

output returns to the High state and ISR[3] is cleared when the

counter is stopped by a stop counter command. The CPU may

change the values of CTPU and CTPL at any time, but the new

count becomes effective only on the next start counter commands.

If new values have not been loaded, the previous count values are

preserved and used for the next count cycle

In the counter mode, the current value of the upper and lower 8 bits

of the counter (CTU, CTL) may be read by the CPU. It is

recommended that the counter be stopped when reading to prevent

potential problems which may occur if a carry from the lower 8 bits

to the upper 8 bits occurs between the times that both halves of the

counter are read. However, note that a subsequent start counter

command will cause the counter to begin a new count cycle using

the values in CTPU and CTPL.

When the C/T clock divided by 16 is selected, the maximum divisor

becomes 1,048,575.

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