SC26C92 datasheet(12/31 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

the value in CTU and CTL and then restarted on the next C/T clock.

If the C/T is allowed to end the count before a new character has

been received, the counter ready bit, ISR[3], will be set. If IMR[3] is

set, this will generate an interrupt. Receiving a character after the

C/T has timed out will clear the counter ready bit, ISR[3], and the

interrupt. Invoking the ‘Set Timeout Mode On’ command, CRx = ‘Ax’,

will also clear the counter ready bit and stop the counter until the

next character is received.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e., an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

The CTS, RTS, CTS Enable Tx signals

CTS (Clear To Send) is usually meant to be a signal to the transmit-

ter meaning that it may transmit data to the receiver. The CTS input

is on pin IP0 or IP1 for the transmitter. The CTS signal is active low;

thus, it is called CTSN. RTS is usually meant to be a signal from the

receiver indicating that the receiver is ready to receive data. It is

also active low and is, thus, called RTSN. RTSN is on pin OP0 or

OP1. A receiver’s RTS output will usually be connected to the CTS

input of the associated transmitter. Therefore, one could say that

RTS and CTS are different ends of the same wire!

MR2(4) is the bit that allows the transmitter to be controlled by the

CTS pin ( IP0 or IP1). When this bit is set to one AND the CTS

input is driven high, the transmitter will stop sending data at the end

of the present character being serialized. It is usually the RTS out-

put of the receiver that will be connected to the transmitter’s CTS

input. The receiver will set RTS high when the receiver FIFO is full

AND the start bit of the ninth character is sensed. Transmission

then stops with nine valid characters in the receiver. When MR2(4)

is set to one, CTSN must be at zero for the transmitter to operate. If

MR2(4) is set to zero, the IP0 or IP1 pin will have no effect on the

operation of the transmitter.

MR1(7) is the bit that allows the receiver to control OP0 or OP1.

When OP0 or OP1 is controlled by the receiver, the meaning of that

pin will be RTS. However, a point of confusion arises in that these

pins may also be controlled by the transmitter. When the transmit-

ter is controlling them the meaning is not RTS at all. It is, rather, that

the transmitter has finished sending its last data byte.

Programming the OP0 or OP1 pin to be controlled by the receiver

and the transmitter at the same time is allowed, but would usually be

incompatible.

RTS can also be controlled by the commands 1000 and 1001 in the

command register. RTS is expressed at the OP0 or OP1 pin which

is still an output port. Therefore, the state of OP0 or OP1 should be

set low (either by commands of the CR register or by writing to the

SOPR or ROPR (Set or Reset Output Port Registers) for the receiv-

er to generate the proper RTS signal. The logic at the output is

basically a NAND of the bit in OPR(0) or OPR(1) register and the

RTS signal as generated by the receiver. When the RTS flow con-

trol is selected via the MR1(7) bit the state of the OPR(0) or OPR(1)

the MR registers) will return the OP pins pin to the control of the

OPR register.

Multidrop Mode (9-bit or Wake-Up)

The DUART is equipped with a wake up mode for multidrop

applications. This mode is selected by programming bits MR1A[4:3]

or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this

mode of operation, a ‘master’ station transmits an address character

followed by data characters for the addressed ‘slave’ station. The

slave stations, with receivers that are normally disabled, examine

the received data stream and ‘wakeup’ the CPU (by setting RxRDY)

only upon receipt of an address character. The CPU compares the

received address to its station address and enables the receiver if it

wishes to receive the subsequent data characters. Upon receipt of

another address character, the CPU may disable the receiver to

initiate the process again.

A transmitted character consists of a start bit, the programmed

number of data bits, and Address/Data (A/D) bit, and the

programmed number of stop bits. The polarity of the transmitted

A/D bit is selected by the CPU by programming bit

MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the

A/D bit position, which identifies the corresponding data bits as data

while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,

which identifies the corresponding data bits as an address. The

CPU should program the mode register prior to loading the

corresponding data bits into the TxFIFO.

In this mode, the receiver continuously looks at the received data

stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one (address tag), but discards the received

character if the received A/D bit is a zero (data tag). If enabled, all

received characters are transferred to the CPU via the RxFIFO. In

either case, the data bits are loaded into the data FIFO while the

A/D bit is loaded into the status FIFO position normally used for

parity error (SRA[5] or SRB[5]). Framing error, overrun error, and

break detect operate normally whether or not the receive is enabled.

PROGRAMMING

The operation of the DUART is programmed by writing control words

into the appropriate registers. Operational feedback is provided via

status registers which can be read by the CPU. The addressing of

the registers is described in Table 1.

The contents of certain control registers are initialized to zero on

RESET. Care should be exercised if the contents of a register are

changed during operation, since certain changes may cause

operational problems.

For example, changing the number of bits per character while the

transmitter is active may cause the transmission of an incorrect

character. In general, the contents of the MR, the CSR, and the

OPCR should only be changed while the receiver(s) and

transmitter(s) are not enabled, and certain changes to the ACR

should only be made while the C/T is stopped.

Each channel has 3 mode registers (MR0, 1, 2) which control the

basic configuration of the channel. Access to these registers is

controlled by independent MR address pointers. These pointers are

set to 0 or 1 by MR control commands in the command register

“Miscellaneous Commands”. Each time the MR registers are

accessed the MR pointer increments, stopping at MR2. It remains

pointing to MR2 until set to 0 or 1 via the miscellaneous commands

of the command register. The pointer is set to 1 on reset for

compatibility with previous Philips Semiconductors UART software.

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