SC26C92 datasheet(11/31 Pages) PHILIPS

11 / 31 page

Philips Semiconductors

Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

seen. At this point the host has approximately 6/16–bit time to read

a byte from the RxFIFO or the overrun condition will be set. The

10th character then overruns the 9th and the 11th the 10th and so on

until an open position in the RxFIFO is seen. (“seen” meaning at

least one byte was read from the RxFIFO.)

Overrun is cleared by a use of the “error reset” command in the

command register.

The fundamental meaning of the overrun is that data has been lost.

Data in the RxFIFO remains valid. The receiver will begin placing

characters in the RxFIFO as soon as a position becomes vacant.

Note: Precaution must be taken when reading an overrun FIFO.

There will be 8 valid characters in the receiver FIFO. There will

be one character in the receiver shift register. However it will

NOT be known if more than one “over–running” character has

been received since the overrun bit was set. The 9th character

is received and read as valid but it will not be known how many

characters were lost between the two characters of the 8th and

9th reads of the RxFIFO

The ”Change of break” means that either a break has been detected

or that the break condition has been cleared. This bit is available in

the ISR. The break change bit being set in the ISR and the received

break bit being set in the SR will signal the beginning of a break. At

the termination of the break condition only the change of break in

the ISR will be set. After the break condition is detected the ter-

mination of the break will only be recognized when the RxD input

has returned to the high state for two successive edges of the 1x

clock; 1/2 to 1 bit time (see above).

The receiver is disabled by reset or via CR commands. A disabled

receiver will not interrupt the host CPU under any circumstance in

the normal mode of operation. If the receiver is in the multi–drop or

special mode, it will be partially enabled and thus may cause an

interrupt. Refer to section on Wake–Up and the register description

for MR1 for more information.

Receiver Status Modes (block and character)

In addition to the data word, three status bits (parity error, framing

error, and received break) are also appended to each data character

in the FIFO (overrun is not). Status can be provided in two ways, as

programmed by the error mode control bit in the mode register. In

the ‘character’ mode, status is provided on a character–by–charac-

ter basis; the status applies only to the character at the top of the

FIFO. In the ‘block’ mode, the status provided in the SR for these

three bits is the logical–OR of the status for all characters coming to

the top of the FIFO since the last ‘reset error’ command was issued.

In either mode reading the SR does not affect the FIFO. The FIFO

is ‘popped’ only when the RxFIFO is read. Therefore the status

Receiver Flow Control

The receiver can control the deactivation of RTS. If programmed to

operate in this mode, the RTSN output will be negated when a valid

start bit was received and the FIFO is full. When a FIFO position

becomes available, the RTSN output will be re–asserted automati-

cally. This feature can be used to prevent an overrun, in the receiv-

er, by connecting the RTSN output to the CTSN input of the

transmitting device.

Note: The transmitter may also control the “RTSN” pin. When

under transmitter control the meaning is completely changed.

The meaning is the transmission has ended. This signal is

usually used to switch (turnaround) a bi–directional driver from

transmit to receive.

If the receiver is disabled, the FIFO characters can be read. Howev-

er, no additional characters can be received until the receiver is

enabled again. If the receiver is reset, the FIFO and all of the re-

ceiver status, and the corresponding output ports and interrupt are

reset. No additional characters can be received until the receiver is

enabled again.

Receiver Reset and Disable

Receiver disable stops the receiver immediately – data being

assembled in the receiver shift register is lost. Data and status in

the FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected. A receiver reset will discard

the present shift register date, reset the receiver ready bit (RxRDY),

clear the status of the byte at the top of the FIFO and re-align the

FIFO read/write pointers.

A ‘watchdog timer’ is associated with each receiver. Its interrupt is

enabled by MR0[7]. The purpose of this timer is to alert the control

processor that characters are in the RxFIFO which have not been

read and/or the data stream has stopped. This situation may occur

at the end of a transmission when the last few characters received

are not sufficient to cause an interrupt.

This counter times out after 64 bit times. It is reset each time a

character is transferred from the receiver shift register to the

RxFIFO or a read of the RxFIFO is executed.

Receiver Timeout Mode

In addition to the watch dog timer described in the receiver section,

the counter/timer may be used for a similar function. Its

programmability, of course, allows much greater precision of time

out intervals.

The timeout mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

is not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTU and CTL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new

data during the programmed time interval, the counter ready bit will

get set, and an interrupt can be generated.

The timeout mode is enabled by writing the appropriate command to

the command register. Writing an ‘Ax’ to CRA or CRB will invoke

the timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will

disable the timeout mode. The timeout mode should only be used

by one channel at once, since it uses the C/T. If, however, the

timeout mode is enabled from both receivers, the timeout will occur

only when both receivers have stopped receiving data for the

timeout period. CTU and CTL must be loaded with a value greater

than the normal receive character period. The timeout mode

disables the regular START/STOP Counter commands and puts the

C/T into counter mode under the control of the received data stream.

Each time a received character is transferred from the shift register

to the RxFIFO, the C/T is stopped after 1 C/T clock, reloaded with

SC26C92 датащи(PDF) 11 Page - NXP Semiconductors

SC26C92 датащи(HTML) 11 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

датащи скачать

ссылки URL