SC26C92 datasheet(16/31 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

CTPU

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CTPU

0x06

C/T[15]

C/T[14]

C/T[13]

C/T[12]

C/T[11]

C/T[10]

C/T[9]

C/T[8]

0x06

CTPL

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CTPL

0x07

C/T[7]

C/T[6]

C/T[5]

C/T[4]

C/T[3]

C/T[2]

C/T[1]

C/T[0]

0x07

MR0 is accessed by setting the MR pointer to 0 via the command

MR0A

MR0[7] – This bit controls the receiver watch dog timer. 0 = disable,

1 = enable. When enabled, the watch dog timer will generate a

receiver interrupt if the receiver FIFO has not been accessed within

64 bit times of the receiver 1X clock. This is used to alert the control

processor that data is in the RxFIFO that has not been read. This

situation may occur when the byte count of the last part of a

message is not large enough to generate an interrupt.

MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit

6 of MR1 sets the fill level of the 8 byte FIFO that generates the

receiver interrupt.

Table 3.

Receiver FIFO Interrupt Fill Level

MR0[6]

MR1[6]

Interrupt Condition

1 or more bytes in FIFO

(Rx RDY)

3 or more bytes in FIFO

6 or more bytes in FIFO

8 bytes in FIFO

(Rx FULL)

For the receiver these bits control the number of FIFO positions

empty when the receiver will attempt to interrupt. After the reset the

receiver FIFO is empty. The default setting of these bits cause the

receiver to attempt to interrupt when it has one or more bytes in it.

MR0[5:4] – Tx interrupt fill level.

Table 4.

Transmitter FIFO Interrupt Fill Level

MR0[5]

MR0[4]

Interrupt Condition

8 bytes empty

(Tx EMPTY)

4 or more bytes empty

6 or more bytes empty

1 or more bytes empty

(Tx RDY)

For the transmitter these bits control the number of FIFO positions

empty when the receiver will attempt to interrupt. After the reset the

transmit FIFO has 8 bytes empty. It will then attempt to interrupt as

soon as the transmitter is enabled. The default setting of the MR0

bits (00) condition the transmitter to attempt to interrupt only when it

is completely empty. As soon as one byte is loaded, it is no longer

empty and hence will withdraw its interrupt request.

MR0[3] – Not used. Should be set to 0.

MR0[2:0] – These bits are used to select one of the six baud rates

(see Table 5).

000

Normal mode

001

Extended mode I

100

Extended mode II

Other combinations should not be used

Note: MR0[3:0] are not used in channel B and should be set to 0.

MR1A

MR1A is accessed when the Channel A MR pointer points to MR1.

The pointer is set to MR1 by RESET or by a ‘set pointer’ command

applied via CR command 1. After reading or writing MR1A, the

pointer will point to MR2A.

MR1A[7] – Channel A Receiver Request-to-Send Control

(Flow Control)

This bit controls the deactivation of the RTSAN output (OP0) by the

receiver. This output is normally asserted by setting OPR[0] and

negated by resetting OPR[0].

MR1A[7] = 1 causes RTSAN to be negated (OP0 is driven to a ‘1’

[VCC]) upon receipt of a valid start bit if the Channel A FIFO is full.

This is the beginning of the reception of the ninth byte. If the FIFO is

not read before the start of the tenth byte, an overrun condition will

occur and the tenth byte will be lost. However, the bit in OPR[0] is

not reset and RTSAN will be asserted again when an empty FIFO

position is available. This feature can be used for flow control to

prevent overrun in the receiver by using the RTSAN output signal to

control the CTSN input of the transmitting device.

MR1[6] – Bit 1 of the receiver interrupt control. See description

under MR0[6].

MR1A[5] – Channel A Error Mode Select

This bit select the operating mode of the three FIFOed status bits

(FE, PE, received break) for Channel A. In the ‘character’ mode,

status is provided on a character-by-character basis; the status

applies only to the character at the top of the FIFO. In the ‘block’

mode, the status provided in the SR for these bits is the

accumulation (logical-OR) of the status for all characters coming to

the top of the FIFO since the last ‘reset error’ command for Channel

A was issued.

MR1A[4:3| – Channel A Parity Mode Select

If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data MR1A[4:3] = 11 selects Channel A to operate in the

special multidrop mode described in the Operation section.

MR1A[2] – Channel A Parity Type Select

This bit selects the parity type (odd or even) if the ‘with parity’ mode

is programmed by MR1A[4:3], and the polarity of the forced parity bit

if the ‘force parity’ mode is programmed. It has no effect if the ‘no

parity’ mode is programmed. In the special multidrop mode it

selects the polarity of the A/D bit.

MR1A[1:0] – Channel A Bits Per Character Select

This field selects the number of data bits per character to be

transmitted and received. The character length does not include the

start, parity, and stop bits.

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