SAA7380GP datasheet(21/60 Pages) PHILIPS

21 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

Table 17 HSEL bits

7.7.19

SUB_L, SUB_H

This 10-bit register specifies the memory address of the subcode data block. This address will always be in the first

1 kbyte of memory.

7.7.20

INCNF

This register is used to specify the configuration of the input data path.

Table 18 INCNF register bits

Note

1. For subcode Q-to-W recovery, the BCK clock is used as a timing reference. It is possible to recover the Q-to-W

subcode using the SAA7380, while at the same time the serial interface is programmed in oversampling mode for a

DAC. Under such circumstances, it is necessary to tell the SAA7380 the oversampling factor.

HSEL CONTENT

SELECTED HOST

INTERFACE

DESCRIPTION

BIT 2

BIT 1

BIT 0

Sanyo

Sanyo compatible mode

ATAPI

ATAPI Mode

Oak

Oak compatible mode

unknown host

all host bus pins 3-state, default after h/w reset

others

reserved

for future enhancements

BIT

NAME

DESCRIPTION

IISmode

I2S-bus mode = 0; EIAJ serial interface mode = 1.

div1(1)

If div1 and div0 = logic 0 then no oversampling (normal CDROM modes); If div1 = logic 0

and div0 = logic 1 then 2 times oversampling; If div1 = logic 1 and div0 = logic 0 then

4 times oversampling.

div0(1)

If div1 and div0 = logic 0 then no oversampling (normal CDROM modes); If div0 = logic 1

and div1 = logic 0 then 2 times oversampling; If div1 = logic 0 and div1 = logic 0 then

4 times oversampling.

QWmode

Selection of Q-to-W input format. Logic 0 = V4 mode; logic 1 = EIAJ mode.

QWon

Q-to-W interface enable. Logic 0 = off; logic 1 = on.

QWcook

Q-to-W interface cooking enable. Logic 0 = cooked mode; logic 1 = RAW mode.

RAMtest

External RAM test mode. Logic 0 = normal operation; logic 1 = RAM test mode.

−−

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