SAA7380GP datasheet(18/60 Pages) PHILIPS

18 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

7.7.14

STAT0

Resetting the chip clears all bits in this register.

Table 9

STAT0 register bits

7.7.15

STAT1

Resetting the chip clears all bits in this register.

The bits in this register indicate the reliability of data in the HEAD0 to HEAD3 registers. Bits MINERR, SECERR,

BLKERR and MODERR indicate errors in the minutes, seconds, frames and mode bytes in the header of the current

block. Bits SH0ERR to SH3ERR indicate errors in the respective bytes in the sub-header.

Table 10 STAT1 register bits

BIT

NAME

FUNCTION

CRCOK

Cyclic redundancy check not OK = 0; Cyclic redundancy check OK = 1. Set by the

EDC in accordance with the results of the CRC check.

ILSYNC

Sync pattern detected at word count 0 to 1174 or 1176 onwards = 1. This bit is set to

logic 1 if the sync pattern in the incoming data is detected between word counts

0 and 1174 or 1176 to infinity, and the decoder has been retimed. Due to the

presence of the cache RAM, it is necessary to stop error correction also when long

blocks have been detected.

NOSYNC

Sync pattern inserted by sync interpolator not coincident with data sync = 1. This bit

is set to logic 1, if the word counter reaches 1175 and no sync pattern has been

detected in the input data. It indicates that the sync interpolator circuit inserted a

sync.

LBLK

With SYIEN = 0, no sync found. Data block size has been extended = 1. This bit is

set to logic 1, if the sync interpolator was switched off, and if the sync interpolator

indicated that sync insertion was necessary. This condition causes the block length to

be extended.

Reserved

SBLK

Short block indication = 1. This bit is set to logic 1 if the decoder is not retimed when

a sync pattern is detected in an incorrect word location, and is ignored while the

SYDEN bit is set to logic 0.

ERABLK

One or more bytes of the block are ﬂagged with C2 ﬂags = 1. This bit is set to logic 1

if one or more bytes of the current block contain erasures as indicated by the C2PO

input.

UCEBLK

Uncorrectable errors in block = 1. This bit is set to logic 1 when one or more bytes of

the current block remain in error after the error correction process.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MINERR

SECERR

BLKERR

MODER

SH0ERR

SH1ERR

SH2ERR

SH3ERR

SAA7380GP датащи(PDF) 18 Page - NXP Semiconductors

SAA7380GP датащи(HTML) 18 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL