SAA7380GP datasheet(13/60 Pages) PHILIPS

13 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

7.7

7.7.1

SBOUT/ADATA

This is a 12 byte FIFO used to transfer data from the

sub-CPU to the host.

In the Sanyo and Oak compatibility mode writing to this

SOUTEN bit in the IFCTRL register has been set to logic 1,

writing to the SBOUT register sets the STBSY bit to

logic 0. If the STWAI bit is set to logic 0, STEN is

immediately set LOW to inform the host computer that the

status byte is ready to be read from.

If the STWAI bit is set to logic 1 and the DTEN bit in the

IFSTAT register is also set to logic 1, both the STEN pin

and the STBSY will go LOW. However, if the STWAI bit is

set to logic 0, and the DTEN bit is set to logic 0, then STEN

is held HIGH until the DTEN bit goes HIGH, thereafter it

goes LOW.

7.7.2

COMIN/ APCMD

During the ATAPI mode this register is used to read the

program command sent by the host. The program

command can only be received if the appropriate mode

has been selected (see Table 22) and a data transfer has

been started (see DTRG register).

During Sanyo and Oak compatibility modes this register is

a 12 byte FIFO which is used to transfer commands from

the host to the sub-CPU. If reading this register empties

the command FIFO then CMDI is set to logic 1 and further

reads from the register will return FFH.

7.7.3

IFCTRL

The IFCTRL register provides control over the host

interface. Resetting the chip will clear all bits. In the ATAPI

mode, only, bits 7 to 5 have any effect.

Table 3

IFCTRL register bits

BIT

NAME

DESCRIPTION

CMDIEN

Enable bits for CMDI, DTEI and DECI. These are interrupt masks, enabling/disabling the

sub-CPU interrupt pin. They do not affect the bits in the IFSTAT register. If set to logic 1,

the corresponding interrupt is enabled. It should be noted that these masks do not clear

the interrupts.

DTEIEN

DECIEN

CMDBK

Command break enable. If set to logic 0 then the command break function is enabled

and if the host writes to the COMIN FIFO then any data or status byte transfers in

progress will be terminated. If set to logic 1 then this operation is disabled. The data

transfer interrupt DTEI is not generated by a command break.

DTWAI

Data transfer WAIT enable. Setting this bit to logic 0 enables the data WAIT function.

The data WAIT function allows the SAA7380 to delay hardware execution of the data

transfer until a status byte transfer has been completed. Disabling the data WAIT

function allows data transfers to take place independently of status byte transfers.

STWAI

Status byte transfer WAIT enable. This bit acts in a similar way to the DTWAI bit except it

controls the status WAIT function. The status WAIT function allows the SAA7380 to

delay hardware execution of the status transfer until a data byte transfer has been

completed. Disabling the data WAIT function allows status transfers to take place

independently of data transfers.

DOUTEN

Data output enable. DOUTEN enables/disables data transfers. When set to logic 0, all

data transfers in progress are aborted.

SOUTEN

Status output enable. SOUTEN enables/disables status byte transfers. When set to

logic 0, the status FIFO register is reset to empty and all status byte transfers in progress

are aborted.

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