SAA7380GP datasheet(6/60 Pages) PHILIPS

6 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

DGND4

−

digital ground 4

CS1/HEN

host interface enable input (active LOW)

HWR

host interface write enable input (active LOW)

HRD

host interface read enable input (active LOW)

DMACK

DMA acknowledge input

IORDY/WAIT/HFBLB

host interface wait output (active LOW); 3-state control

SCRST/STEN

host interface status enable output ATAPI sub-CPU reset signal

(active LOW)

DMARQ/DTEN

ATAPI DMA request host interface data enable output (active LOW);

3-state control

IRQ/EOP/HFBC

host interface end of process ﬂag output ATAPI host interrupt request

(active LOW); 3-state control

VDDD2

−

digital supply voltage 2 (5 V)

HD0

I/O

host interface data bus input/output line 0

HD1

I/O

host interface database input/output line 1

HD2

I/O

host interface database input/output line 2

HD3

I/O

host interface data bus input/output line 3

HD4

I/O

host interface data bus input/output line 4

HD5

I/O

host interface data bus input/output line 5

HD6

I/O

host interface data bus input/output line 6

HD7

I/O

host interface data bus input/output line 7

DGND5

−

digital ground 5

HD8

I/O

host interface data bus input/output line 8

HD9

I/O

host interface data bus input/output line 9

HD10

I/O

host interface data bus input/output line 10

HD11

I/O

host interface data bus input/output line 11

HD12

I/O

host interface data bus input/output line 12

HD13

I/O

host interface data bus input/output line 13

HD14

I/O

host interface data bus input/output line 14

HD15

I/O

host interface data bus input/output line 15

DGND6

−

digital ground 6

DA0/CMD

host interface data input (active LOW)/command select input host interface

address line 0

DA1

ATAPI address line input 1

DA2/EJECT

ATAPI address line input 2

CS2/SELRQ

ATAPI chip select input 2

IOCS16

ATAPI 16-bit data select output

VDDD2

−

digital supply voltage 2 (5 V)

RA0

buffer RAM address bus output line 0

RA1

buffer RAM address bus output line 1

RA2

buffer RAM address bus output line 2

SYMBOL

I/O

DESCRIPTION

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