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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SAA7380GP датащи(PDF) 42 Page - NXP Semiconductors |
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SAA7380GP датащи(HTML) 42 Page - NXP Semiconductors |
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42 / 60 page  1996 Apr 25 42 Philips Semiconductors Preliminary specification Error correction and host interface IC for CD-ROM (ELM) SAA7380 Notes 1. All timings are for single-speed, they should be divided by the speed up to eight times speed. 2. T represents half a clock period. 3. The timings for this mode can only be met with a 33 MHz clock. 4. CLK = 1 clock period. t7 HWR/HRD inactive 33 MHz clock 60 −− ns 16 MHz clock 145 −− ns t8 HWR data set-up 50 −− ns t9 HWR data hold 20 −− ns t10 HRD data access −− 80 ns t11 HRD data to 3-state 5 − 60 ns t12 cycle time 3CLK −− ns 8-BIT DMA DATA TRANSFER; see Fig.23 t0 DMARQ to DMACK 0 −− ns t1 HWR/HRD to DMARQ inactive −− 80 ns t2 DMACK set-up 30 −− ns t3 DMACK hold 0 −− ns t4 HWR/HRD active 33 MHz clock 50 −− ns 16 MHz clock 75 −− ns t5 HWR/HRD inactive 33 MHz clock 60 −− ns 16 MHz clock 145 −− ns t6 HWR data set-up 50 −− ns t7 HWR data hold 20 −− ns t8 HRD data access −− 80 ns t9 HRD data to 3-state −− 60 ns PSEUDO 16-BIT DMA READ TRANSFER; see Fig.24; note 4 t0 HRD to DMARQ inactive −− 80 ns t1 DMARQ to DMACK 0 −− ns t2 HRD inactive to DMACK inactive 0 −− ns t3 HRD active 33 MHz clock 50 −− ns 16 MHz clock 65 −− ns t4 HFBC to data valid −− CLK ns t5 data 3-state to HFBC inactive CLK −− ns t6 HRD data access −− 80 ns t7 HRD data to 3-state −− 60 ns t8 HFBC active −− 5CLK ns t9 data valid to HFBLB 2CLK −− ns t10 HFBLB to HFBC inactive 2CLK −− ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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