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MPC5200B датащи(PDF) 17 Page - Freescale Semiconductor, Inc

номер детали MPC5200B
подробное описание детали  SDRAM/DDR Memory Controller
PDF  78 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200B датащи(HTML) 17 Page - Freescale Semiconductor, Inc

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Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 1
Freescale Semiconductor
17
NOTES:
Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter to prevent them from getting into the
chip.
HRESET and SRESET must have a monotonous rise time.
The assertion of HRESET becomes active at Power on Reset without any SYS_XTAL clock.
For additional information, see the MPC5200B User Manual [1].
3.3.3.1
Reset Configuration Word
During reset (HRESET and PORRESET) the Reset Configuration Word is latched in the related Reset
Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and
PORRESET) are inactive (high), the contents of this register will be locked immediately with the
SYS_XTAL clock (see Figure 3).
Figure 3. Reset Configuration Word Locking
Table 15. Reset Rise / Fall Timing
Description
Min
Max
Unit
SpecID
PORRESET fall time
—
1
ms
A3.4
PORRESET rise time
—
1
ms
A3.5
HRESET fall time
—
1
ms
A3.6
HRESET rise time
—
1
ms
A3.7
SRESET fall time
—
1
ms
A3.8
SRESET rise time
—
1
ms
A3.9
sample
sample
sample
sample
sample
sample
sample
sample
sample
sample
LOCK
RST_CFG_WRD
HRESET
PORRESET
SYS_XTAL
4096 clocks



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