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MPC5200B датащи(PDF) 43 Page - Freescale Semiconductor, Inc

номер детали MPC5200B
подробное описание детали  SDRAM/DDR Memory Controller
PDF  78 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200B датащи(HTML) 43 Page - Freescale Semiconductor, Inc

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Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 1
Freescale Semiconductor
43
Figure 29. Ethernet Timing Diagram—MII Async
Figure 30. Ethernet Timing Diagram—MII Serial Management
Table 34. MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t10
MDC falling edge to MDIO output delay
0
25
ns
A9.10
t11
MDIO (input) to MDC rising edge setup
10
—
ns
A9.11
t12
MDIO (input) to MDC rising edge hold
10
—
ns
A9.12
t13
MDC pulse width high(1)
NOTES:
1
MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED
control register is changed during operation. See the MPC5200B User Manual [1].
160
—
ns
A9.13
t14
MDC pulse width low(1)
160
—
ns
A9.14
t15
MDC period(2)
2
The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5200B User Manual [1].
400
—
ns
A9.15
t9
CRS, COL
t14
t13
t12
MDC (Output)
MDIO (Input)
MDIO (Output)
t11
t10
t15



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