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MPC5200B датащи(PDF) 47 Page - Freescale Semiconductor, Inc |
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MPC5200B датащи(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 78 page ![]() Electrical and Thermal Characteristics MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 47 NOTE Output timing is specified at a nominal 50 pF load. Figure 34. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 Cycle time 4 1024 IP-Bus Cycle(1) NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1]. A11.21 2 Clock high or low time 2 512 IP-Bus Cycle(1) A11.22 3 Slave select to clock delay 15.0 — ns A11.23 4 Output data valid — 20.0 ns A11.24 5 Input Data setup time 20.0 — ns A11.25 6 Input Data hold time 20.0 — ns A11.26 7 Slave disable lag time 15.0 — ns A11.27 8 Sequential Transfer delay 1 — IP-Bus Cycle(1) A11.28 9 Clock falling time — 7.9 ns A11.29 10 Clock rising time — 7.9 ns A11.30 SCK (CLKPOL=0) SCK (CLKPOL=1) MOSI Output Output Output SS Output MISO Input 1 22 7 8 3 4 6 10 9 9 10 5 |
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