MPC5200B datasheet(71/78 Pages) FREESCALE

71 / 78 page

System Design Information

MPC5200B Data Sheet, Rev. 1

Freescale Semiconductor

PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and

PCI_REQ.

5.3.3

Pull-up/Pull-down Requirements for MEM_MDQS Pins

(SDRAM)

The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down

resistors in SDRAM mode.

5.3.4

Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR

16-bit Mode)

The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.

5.4

JTAG

The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also

provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The

COP Interface provides access to the MPC5200B's embedded Freescale (formerly Motorola) MPC603e

e300 processor. This interface provides a means for executing test routines and for performing software

development and debug functions.

5.4.1

JTAG_TRST

Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional

in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC

architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted

during power-on reset.

5.4.1.1

JTAG_TRST and PORRESET

The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The

JTAG module must be reset before the MPC5200B comes out of power-on reset; do this by asserting

JTAG_TRST before PORRESET is released.

For more details refer to the Reset and JTAG Timing Specification.

MPC5200B датащи(PDF) 71 Page - Freescale Semiconductor, Inc