IA186EM-PQF100I-R datasheet(67/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

rxd (pio28) - Receive Data (asynchronous input)

This signal connects asynchronous serial receive data from the system to the asynchronous serial port.

s2_n-s0_n - Bus Cycle Status (synchronous outputs with tristate)

These three signals inform the system of the type of bus cycle is in progress. s2_n may be used to

indicate whether the current access is to memory or I/O, and s1_n may be used to indicate whether data is

being transmitted or received. These signals are tristated during bus hold and hold acknowledge.

The coding for these pins is shown in the following table.

s2_n

s1_n

s0_n

Bus Cycle

Interrupt acknowledge

Read data from I/O

Write data to I/O

Halt

Instruction fetch

Read data from memory

Write data to memory

None (passive)

s6/clkdiv2_n (pio29) - Bus Cycle Status Bit 6 (synchronous output) /Clock Divide by 2 (input with

internal pull-up)

s6 - This signal is high during the second and remaining cycle periods, i.e. t2 – t4, indicating that a DMA–

initiated bus cycle is under way. s6 is tristated during bus hold or reset.

clkdiv2_n – The microcontroller enters clock divide-by-2 mode, if this signal is held low during power-

on-reset. In this mode, the PLL is disabled and the processor receives the external clock divided by 2.

Sampling of this pin occurs on the rising edge of res_n.

Should this pin be used as pio29 configured as an input, care should be taken that it is not driven low

during power-on-reset. This pin has an internal pull-up so it is not necessary to drive the pin high even

though it defaults to an input PIO.

sclk – Serial Clock (synchronous outputs with tristate)

This pin provides a slave device with a synchronous serial clock permitting synchronization of the

transmit and receive data exchanges between the slave and the microcontroller. sclk is the result of

dividing the internal clock by 2, 4, 8, or 16 dependent on the contents of the Synchronous Serial Control

(SSC) register bits 5-4. Accessing either the SSR of SSD registers activates the sclk for eight cycles.

When sclk is not active the microcontroller hold is high.

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IA186EM-PQF100I-R датащи(PDF) 67 Page - InnovASIC, Inc