IA186EM-PQF100I-R datasheet(37/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

The value of these registers is 000Fh at reset.

5 4

Reserved

MSK

PR2 - PR0

Reserved (bits 15-4) – Set to 0.

MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The

interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a

duplicate of this bit.

PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to

other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are

shown in the above table (Priority Level).

DMA1CON/INT6CON (036h) – DMA and INTerrupt CONtrol Register. DMA0CON/INT5CON (034h)

Master Mode

The DMA0 and DMA1 interrupts have interrupt type 0ah and 0bh respectively. These pins are

configured as external interrupts or DMA requests in the respective DMA Control register.

The value of these registers is 000Fh at reset.

5 4

Reserved

MSK

PR2 - PR0

Reserved (bits 15-4) – Set to 0.

MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The

interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a

duplicate of this bit.

PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to

other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are

shown in the above table (Priority Level).

DMA1CON/INT6 (036h) – DMA and INTerrupt CONtrol Register.

DMA0CON/INT5 (034h)

Slave Mode

The two DMA control registers maintain their original functions and addressing that they possessed in

Master Mode. These pins are configured as external interrupts or DMA requests in the respective DMA

Control register.

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IA186EM-PQF100I-R датащи(PDF) 37 Page - InnovASIC, Inc