PAC7136 datasheet(15/56 Pages) FREESCALE

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ElectricalCharacteristics

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Freescale Semiconductor

3.8

Clock and Reset Generator

This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and

reset generator.

3.8.1

Oscillator Characteristics

The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing

Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing

Pierce oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET

signal. Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the

oscillation is checked for each start from either power on, STOP or oscillator fail. tCQOUT specifies the

maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation

is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device

also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock

signal is below the Clock Monitor Assert Frequency fCMFA.

Table 19. Oscillator Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

J1a

C Crystal oscillator range (loop controlled Pierce)

fOSC

NOTES:

1. If CLKSEL[PLLSEL] is clear then the system clock (fSYS) is equal to fOSC, otherwise it is equal to fVCO (table

Table 20, K3). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.

4.0

—

MHz

J1b

C Crystal oscillator range (full swing Pierce) 2 3

2. Depending on the crystal; a damping series resistor might be necessary

3. XCLKS asserted (low) during reset

fOSC

0.5

—

MHz

P Startup Current

IOSC

100

—

μA

C Oscillator start-up time (loop controlled Pierce)

tUPOSC

—3 4

4. fOSC = 4 MHz, C = 22 pF (refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for circuit

board layout recommendations, including oscillator capacitor placement and values).

50 5

5. Maximum value is for extreme cases using high Q, low frequency crystals

D Clock Quality check time-out

tCQOUT

0.45

—

2.5

P Clock Monitor Failure Assert Frequency

fCMFA

100

200

KHz

P External square wave input frequency 3

fEXT

0.5

—

MHz

D External square wave pulse width low

tEXTL

9.5

—

D External square wave pulse width high

tEXTH

9.5

—

D External square wave rise time

tEXTR

——

J10

D External square wave fall time

tEXTF

——

J11

D Input Capacitance (EXTAL, XTAL pins)

CIN

—7

—

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