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PAC7136 датащи(PDF) 28 Page - Freescale Semiconductor, Inc

номер детали PAC7136
подробное описание детали  Microcontroller Family Hardware Specifications
PDF  56 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PAC7136 датащи(HTML) 28 Page - Freescale Semiconductor, Inc

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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
28
3.10.3 ATD Timing Specifications
Figure 10. ATD External Trigger Timing Diagram
Table 31. ATD External Trigger Timing Specifications
Num C
Parameter
Symbol
Min
Max
Unit
T1
D ETRIG Period (Level-Sensitive Trigger Mode)
TPERIOD 1 + NCONVn
1
NOTES:
1. NCONVn denotes 8- or 10-bit conversion time (refer to specifications N4, N5, P4 and P5). In order to achieve the
minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.
—
fATDCLK Cycles
T2
D ETRIG Minimum Pulse Width
Edge-Sensitive Trigger Mode
Level-Sensitive Trigger Mode
tPW
1
2
—
—
fATDCLK Cycles
T3
D ETRIG Level Recovery 2
2. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.
tLR
1—
fATDCLK Cycles
T4
D Conversion Start Delay
tDLY
—2
fATDCLK Cycles
Level Sensitive
Low Active
Sequence
Conversion Activity
Complete Flag
Low Active
Sequence
Complete Flag
Conversion Activity
Level Sensitive
Falling Edge Active
Conversion Activity
Edge Sensitive
ETRIG
ANn_x
ETRIG
ASCIF
ANn_x
ETRIG
ASCIF
ANn_x
T2
T1
T4
T4
T2
T4
T4
T4
T3



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