PAC7136 datasheet(53/56 Pages) FREESCALE

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MechanicalInformation

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Freescale Semiconductor

v1.0

14-Sep-04

(continued)

Section 3, “Electrical Characteristics” (continued)

• Section 3.10, “Analog-to-Digital Converter”

— Rev. 0.1 redundant and superfluous content deleted

– Section 3.10.3, “ATD Electrical Specifications,” (included Table 29 and Table 30)

– Table 31, “ATD Performance Specifications” (redundant with v0.1 Table 27 and

Table 28, now Table 29 and Table 30)

— Table 26 updates

– Deleted previous spec M6

– Changed spec N7 and N8 values

— Table 27 updates

– Deleted previous spec N6

– Changed spec P7 and P8 values

– Changed spec P2 and footnote (1) to specify 3.15 V

— Table 28 updates

– Changed spec Q2 parameter classification from T to C and 10 pF and 22 pF values

moved from maximum to typical

— Table 29 updates

– Operating conditions VDDA minimum changed to 4.5 V

–VREF description moved from “conditions” header to new footnote (1)

— Table 30 updates

– Operating conditions VDDA minimum changed to 3.15 V

–VREF description moved from “conditions” header to new footnote (1)

— Table 31 updates

– Spec T1 description clarified, max removed, min added with footnote

– Spec T2 modified to show both edge- and level-sensitive modes

— Figure 10 modified to remove “Max Frequency” label and clearly separate edge- and

level-sensitive mode timing examples

• Section 3.11, “Serial Peripheral Interface”

— Table 32 updates

– Changed specs U1a, U1b and U4 to use fIPS and tIPS for clarity and consistency with

MAC7100RM

– Changed U1a max to ½ and U1b min to 2 to account for the DBR bit

— Table 33 updates

– Changed specs V1a, V1b, V2, V3, V4, V7, V8 to use fIPS and tIPS for clarity and

consistency with MAC7100RM

– Changed V1a max to ½ and V1b min to 2 to account for the DBR bit

• Section 3.13, “Common Flash Module”

— Significant rework to match MAC7100RM clock naming, references and timing

calculations for clarity and consistency

— Changed X1 maximum from 40 MHz to 50 MHz (Table 35)

32 to 35

Revision History (continued)

Version No.

Release Date

Description of Changes

Page

Numbers

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