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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56366 датащи(PDF) 76 Page - Freescale Semiconductor, Inc |
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DSP56366 датащи(HTML) 76 Page - Freescale Semiconductor, Inc |
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76 / 110 page  DSP56366 Technical Data, Rev. 3.1 3-50 Freescale Semiconductor 3.13 Serial Host Interface (SHI) I2C Protocol Timing Table 3-20 SHI I2C Protocol Timing No. Characteristics1,2,3 Symbol/ Expression Standard Mode4 Fast Mode5 Unit Min Max Min Max Tolerable spike width on SCL or SDA Filters bypassed — — 0 — 0 ns Narrow filters enabled — 50 — 50 ns Wide filters enabled — 100 — 100 ns 171 SCL clock frequency FSCL — 100 — 400 kHz 171 SCL clock cycle TSCL 10 — 2.5 — μs 172 Bus free time TBUF 4.7 — 1.3 — μs 173 Start condition set-up time TSU;STA 4.7 — 0.6 — μs 174 Start condition hold time THD;STA 4.0 — 0.6 — μs 175 SCL low period TLOW 4.7 — 1.3 — μs 176 SCL high period THIGH 4.0 — 1.3 — μs 177 SCL and SDA rise time TR — 1000 20 + 0.1 × C b 300 ns 178 SCL and SDA fall time TF — 300 20 + 0.1 × C b 300 ns 179 Data set-up time TSU;DAT 250 — 100 — ns 180 Data hold time THD;DAT 0.0 — 0.0 0.9 μs 181 DSP clock frequency FDSP MHz Filters bypassed 10.6 — 28.5 — Narrow filters enabled 11.8 — 39.7 — Wide filters enabled 13.1 — 61.0 — 182 SCL low to data out valid TVD;DAT — 3.4 — 0.9 μs 183 Stop condition set-up time TSU;STO 4.0 — 0.6 — μs 184 HREQ in deassertion to last SCL edge (HREQ in set-up time) tSU;RQI 0.0 — 0.0 — ns |
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