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DSP56366 датащи(PDF) 70 Page - Freescale Semiconductor, Inc |
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DSP56366 датащи(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 110 page ![]() DSP56366 Technical Data, Rev. 3.1 3-44 Freescale Semiconductor 143 Serial clock low period Master Bypassed 0.5 ×t SPICC –10 38 — ns Narrow 0.5 ×t SPICC –10 91 — ns Wide 0.5 ×t SPICC –10 126.5 — ns Slave Bypassed 2.5 ×T C+12 32.8 — ns Narrow 2.5 ×T C+102 122.8 — ns Wide 2.5 ×T C+189 209.8 — ns 144 Serial clock rise/fall time Master — — — 10 ns Slave — — — 2000 ns 146 SS assertion to first SCK edge CPHA = 0 Slave Bypassed 3.5 ×T C+15 44.2 — ns Narrow 0 0 — ns Wide 0 0 — ns CPHA = 1 Slave Bypassed 10 10 — ns Narrow 0 0 — ns Wide 0 0 — ns 147 Last SCK edge to SS not asserted Slave Bypassed 12 12 — ns Narrow 102 102 — ns Wide 189 189 — ns 148 Data input valid to SCK edge (data input set-up time) Master/Slave Bypassed 0 0 — ns Narrow MAX{(20-TC), 0} 11.7 — ns Wide MAX{(40-TC), 0} 31.7 — ns 149 SCK last sampling edge to data input not valid Master/Slave Bypassed 2.5 ×T C+10 30.8 — ns Narrow 2.5 ×T C+30 50.8 — ns Wide 2.5 ×T C+50 70.8 — ns 150 SS assertion to data out active Slave — 2 2 — ns 151 SS deassertion to data high impedance2 Slave — 9 — 9 ns Table 3-19 Serial Host Interface SPI Protocol Timing (continued) No. Characteristics1 Mode Filter Mode Expression Min Max Unit |
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