DSP56366 datasheet(45/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-19

138

Last CAS deassertion to RAS deassertion6

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

tCRP

2.0

× T

C − 6.0

3.5

× T

C − 6.0

4.5

× T

C − 6.0

6.5

× T

C − 6.0

24.4

47.2

62.4

92.8

—

19.0

37.8

50.3

75.3

—

139

CAS deassertion pulse width

tCP

1.25

× T

C − 4.0

14.9

—

11.6

—

140

Column address valid to CAS assertion

tASC

TC − 4.0

11.2

—

8.5

—

141

CAS assertion to column address not valid

tCAH

1.75

× T

C − 4.0

22.5

—

17.9

—

142

Last column address valid to RAS deassertion

tRAL

× T

C − 4.0

41.5

—

33.5

—

143

WR deassertion to CAS assertion

tRCS

1.25

× T

C − 3.8

15.1

—

11.8

—

144

CAS deassertion to WR assertion

tRCH

0.5

× T

C − 3.7

3.9

—

2.6

—

145

CAS assertion to WR deassertion

tWCH

1.5

× T

C − 4.2

18.5

—

14.6

—

146

WR assertion pulse width

tWP

2.5

× T

C − 4.5

33.5

—

26.8

—

147

Last WR assertion to RAS deassertion

tRWL

2.75

× T

C − 4.3

33.4

—

26.8

—

148

WR assertion to CAS deassertion

tCWL

2.5

× T

C − 4.3

33.6

—

27.0

—

149

Data valid to CAS assertion (write)

tDS

0.25

× T

C − 3.7

0.25

× T

C − 3.0

0.1

—

0.1

—

150

CAS assertion to data not valid (write)

tDH

1.75

× T

C − 4.0

22.5

—

17.9

—

151

WR assertion to CAS assertion

tWCS

TC − 4.3

10.9

—

8.2

—

152

Last RD assertion to RAS deassertion

tROH

2.5

× T

C − 4.0

33.9

—

27.3

—

153

RD assertion to data valid

tGA

1.75

× T

C − 7.5

1.75

× T

C − 6.5

—

19.0

—

15.4

154

RD deassertion to data not valid7

tGZ

0.0

—

0.0

—

155

WR assertion to data active

0.75

× T

C − 0.3

11.1

—

9.1

—

156

WR deassertion to data high impedance

0.25

× T

—3.8

—3.1

1 The number of wait states for Page mode access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 The asynchronous delays specified in the expressions are valid for DSP56366.

4 There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See

Figure 3-11)

Table 3-10

DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 (continued)

No.

Characteristics

Symbol

Expression5

66 MHz

80 MHz

Unit

Min

Max

Min

Max

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