DSP56366 datasheet(33/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

3-7

Mode select hold time

0.0

—

Minimum edge-triggered interrupt request assertion width

5.5

—

Minimum edge-triggered interrupt request deassertion width

5.5

—

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

external memory access address out valid

• Caused by first interrupt instruction fetch

• Caused by first interrupt instruction execution

4.25

× T

C + 2.0

7.25

× T

C + 2.0

37.4

62.4

—

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first interrupt

instruction execution

× T

C + 5.0

88.3

—

Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for level

sensitive fast interrupts5

3.75

× T

C + WS × TC – 10.94

—

Note6

Delay from RD assertion to interrupt request deassertion for

level sensitive fast interrupts5

3.25

× T

C + WS × TC – 10.94

—

Note 6

Delay from WR assertion to interrupt request deassertion for

level sensitive fast interrupts5

• DRAM for all WS

• SRAM WS = 1

• SRAM WS = 2, 3

•

SRAM WS

≥ 4

(WS + 3.5)

× T

C – 10.94

(WS + 3.5)

× T

C – 10.94

(WS + 3)

× T

C – 10.94

(WS + 2.5)

× T

C – 10.94

—

Note 6

Duration for IRQA assertion to recover from Stop state

4.9

—

Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)2, 7

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies No

Stop Delay)

PLC

× ET

C × PDF + (128 K −

PLC/2)

× T

PLC

× ET

C × PDF + (23.75 ±

0.5)

× T

(8.25

± 0.5) × T

—

64.6

—

72.9

Duration of level sensitive IRQA assertion to ensure interrupt

service (when exiting Stop)2, 7

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (OMR Bit 6 = 1)

• PLL is active during Stop (PCTL Bit 17 = 1) (implies no

Stop delay)

PLC

× ET

C × PDF + (128K −

PLC/2)

× T

PLC

× ET

C × PDF + (20.5 ± 0.5)

× T

5.5

× T

—

45.8

—

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)

No.

Characteristics

Expression

Min

Max

Unit

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