DP83848C_07 datasheet(52/82 Pages) NSC

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7.2.3 MII Interrupt Status and Misc. Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since the last read of

this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt

will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indi-

cations in this register will be set even if the interrupt is not enabled

Table 23. MII Interrupt Status and Misc. Control Register (MISR), address 0x12

Reserved

0, RO

RESERVED: Writes ignored, Read as 0

ED_INT

0, RO/COR

Energy Detect interrupt:

1 = Energy detect interrupt is pending and is cleared by the current

read.

0 = No energy detect interrupt pending.

LINK_INT

0, RO/COR

Change of Link Status interrupt:

1 = Change of link status interrupt is pending and is cleared by the

current read.

0 = No change of link status interrupt pending.

SPD_INT

0, RO/COR

Change of speed status interrupt:

1 = Speed status change interrupt is pending and is cleared by the

current read.

0 = No speed status change interrupt pending.

DUP_INT

0, RO/COR

Change of duplex status interrupt:

1 = Duplex status change interrupt is pending and is cleared by

the current read.

0 = No duplex status change interrupt pending.

ANC_INT

0, RO/COR

Auto-Negotiation Complete interrupt:

1 = Auto-negotiation complete interrupt is pending and is cleared

by the current read.

0 = No Auto-negotiation complete interrupt pending.

FHF_INT

0, RO/COR

False Carrier Counter half-full interrupt:

1 = False carrier counter half-full interrupt is pending and is

cleared by the current read.

0 = No false carrier counter half-full interrupt pending.

RHF_INT

0, RO/COR

Receive Error Counter half-full interrupt:

1 = Receive error counter half-full interrupt is pending and is

cleared by the current read.

0 = No receive error carrier counter half-full interrupt pending.

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

ED_INT_EN

0, RW

Enable Interrupt on energy detect event

LINK_INT_EN

0, RW

Enable Interrupt on change of link status

SPD_INT_EN

0, RW

Enable Interrupt on change of speed status

DUP_INT_EN

0, RW

Enable Interrupt on change of duplex status

ANC_INT_EN

0, RW

Enable Interrupt on Auto-negotiation complete event

FHF_INT_EN

0, RW

Enable Interrupt on False Carrier Counter Register half-full event

RHF_INT_EN

0, RW

Enable Interrupt on Receive Error Counter Register half-full event

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