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DP83848C датащи(PDF) 31 Page - National Semiconductor (TI) |
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DP83848C датащи(HTML) 31 Page - National Semiconductor (TI) |
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31 / 82 page ![]() 31 www.national.com 4.3.2 Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83848C implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted pair inputs (refer to Figure 10). The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome cor- rectly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will not be rejected. This checking proce- dure results in the loss of typically three preamble bits at the beginning of each packet. Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset. Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection. 4.3.3 Collision Detection and SQE When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simulta- neously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected. The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected it is reported immediately (through the COL pin). When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10-bit times is generated to indi- cate successful transmission. SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. 4.3.4 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activ- ity once valid data is detected via the squelch function. For 10 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mb/s Full Duplex operation, CRS is asserted only during receive activity. CRS is deasserted following an end of packet. 4.3.5 Normal Link Pulse Detection/Generation The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nomi- nally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. Link pulses are used to check the integrity of the connec- tion with the remote end. If valid link pulses are not received, the link detector disables the 10BASE-T twisted pair transmitter, receiver and collision detection functions. When the link integrity function is disabled (FORCE_LINK_10 of the 10BTSCR register), a good link is forced and the 10BASE-T transceiver will operate regard- less of the presence of link pulses. end of packet start of packet VSQ-(reduced) VSQ- VSQ+(reduced) VSQ+ <150 ns <150 ns >150 ns Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation |
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