DP83848C_07 datasheet(35/82 Pages) NSC

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5.4 Power Feedback Circuit

To ensure correct operation for the DP83848C, parallel

caps with values of 10

µF (Tantalum) and 0.1 µF should be

placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected

to pin 23 (PFBOUT), each pin requires a small capacitor

(.1

µF). See Figure 13 below for proper connections.

5.5 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed

on pin 7 of the device. By default, this pin functions as a

power down input and the interrupt function is disabled.

Setting bit 0 (INT_OE) of MICR (0x11h) will configure the

pin as an active low interrupt output.

5.5.1 Power Down Control Mode

The PWR_DOWN/INT pin can be asserted low to put the

device in a Power Down mode. This is equivalent to setting

bit 11 (Power Down) in the Basic Mode Control Register,

BMCR (0x00h). An external control signal can be used to

drive the pin low, overcoming the weak internal pull-up

resistor. Alternatively, the device can be configured to ini-

tialize into a Power Down state by use of an external pull-

down resistor on the PWR_DOWN/INT pin. Since the

device will still respond to management register accesses,

setting the INT_OE bit in the MICR register will disable the

PWR_DOWN/INT input, allowing the device to exit the

Power Down state.

5.5.2 Interrupt Mechanisms

The interrupt function is controlled via register access. All

interrupt sources are disabled by default. Setting bit 1

(INTEN) of MICR (0x11h) will enable interrupts to be out-

put, dependent on the interrupt mask set in the lower byte

of the MISR (0x12h). The PWR_DOWN/INT pin is asyn-

chronously asserted low when an interrupt condition

occurs. The source of the interrupt can be determined by

reading the upper byte of the MISR. One or more bits in the

MISR will be set, denoting all currently pending interrupts.

Reading of the MISR clears ALL pending interrupts.

Example: To generate an interrupt on a change of link sta-

tus or on a change of energy detect power state, the steps

would be:

— Write 0003h to MICR to set INTEN and INT_OE

— Write 0060h to MISR to set ED_INT_EN and

LINK_INT_EN

— Monitor PWR_DOWN/INT pin

When PWR_DOWN/INT pin asserts low, user would read

the MISR register to see if the ED_INT or LINK_INT bits

are set, i.e. which source caused the interrupt. After read-

ing the MISR, the interrupt bits should clear and the

PWR_DOWN/INT pin will deassert.

5.6 Energy Detect Mode

When Energy Detect is enabled and there is no activity on

the cable, the DP83848C will remain in a low power mode

while monitoring the transmission line. Activity on the line

will cause the DP83848C to go through a normal power up

sequence. Regardless of cable activity, the DP83848C will

occasionally wake up the transmitter to put ED pulses on

the line, but will otherwise draw as little power as possible.

Energy detect functionality is controlled via register Energy

Detect Control (EDCR), address 0x1Dh.

Table 9. 25 MHz Crystal Specification

Parameter

Min

Typ

Max

Units

Condition

Frequency

MHz

Frequency

Tolerance

+50

ppm

Operational Tem-

perature

Frequency

Stability

+50

ppm

1 year aging

Load Capacitance

µF

Pin 23 (PFBOUT)

µF

Pin 18 (PFBIN1)

Pin 37 (PFBIN2)

Figure 13. Power Feeback Connection

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