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READING FROM THE THS7347

THS7347

SLOS531 – MAY 2007

address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an acknowledge from the

THS7347, the master presents the subaddress (channel) of the register it wants to read. After the cycle is

acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).

the THS7347. After the data byte has been transferred from the THS7347 to the master, the master generates a

not-acknowledge (A) followed by a stop. As with the Write function, to read all channels, steps 1 through 11

must be repeated for each channel desired.

THS7347 Read Phase 1:

Step 1

0

S

Step 2

7

6

5

4

3

2

1

0

0

1

0

1

1

X

X

0

Step 3

9

A

Step 4

7

6

5

4

3

2

1

0

0

0

0

0

0

Addr

Addr

Addr

Where Addr is determined by the values shown in Table 2.

Step 5

9

A

Step 6

0

P

THS7347 Read Phase 2:

Step 7

0

S

Step 8

7

6

5

4

3

2

1

0

0

1

0

1

1

X

X

1

Step 9

9

A

Step 10

7

6

5

4

3

2

1

0

Data

Data

Data

Data

Data

Data

Data

Data

Where Data is determined by the logic values contained in the Channel Register.

Step 11

9

A

Step 12

0

P

23

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