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THS7347

SLOS531 – MAY 2007

Table 4. THS7347 Channel Register (H/V Sync Channel + Analog Channels State) Bit Decoder Table.

Use in Conjunction With Register Bit Code (0000 0100)

BIT

BIT

FUNCTION

VALUE(S)

RESULT

(MSB)

Reserved; Do not care

X

Reserved; do not care

7

0

Disables all monitor channels regardless of bits 2:0 of Register 1

Monitor Pass-Through Path Disable

through Register 3

6

Mode

1

Enables monitor channels functions dictated by each programmed

(Use in Conjunction with Table 3)

register code

0

Disables all buffer channels regardless of bits 2:0 of Register 1

through Register 3

Buffer Path Disable Mode

5

(Use in Conjunction with Table 3)

1

Enables buffer channel functions dictated by each programmed

register code

0 0

MUX Input A

0 1

MUX Input B

4, 3

Vertical Sync Channel MUX Selection

1 0

Reserved; do not care

1 1

Reserved; do not care

0 0

MUX Input A

0 1

MUX Input B

2, 1

Horizontal Sync Channel MUX Selection

1 0

Reserved; do not care

1 1

Reserved; do not care

0

Disable H-Sync and V-Sync Channels

0

H/V Sync Paths Disable Mode

(LSB)

1

Enable H-Sync and V-Sync Channels

Bit (MSB) 7: Reserved; do not care.

Bit 6: Master Monitor Path Disable. Disables all monitor channels regardless of what is programmed into

each register channel (1 to 3).

Bit 5: Master Buffer Path Disable. Disables all buffer channels regardless of what is programmed into each

register channel (1 to 3).

Bits 4, 3: Selects the Input MUX channel for the Vertical Sync.

Bits 2, 1: Selects the Input MUX channel for the Horizontal Sync.

Bit 0 (LSB): Enables or disables the H-Sync and V-Sync Channels.

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